lpm_rom0.tan.qmsg

s盒设计源程序 可以用语DES设计

{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[9\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 2.307 ns register " "Info: th for register \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[9\]\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 2.307 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 3.749 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 3.749 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK ELA_X0_Y15_N0 128 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = ELA_X0_Y15_N0; Fanout = 128; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.207 ns) + CELL(0.542 ns) 3.749 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[9\] 2 REG LC_X7_Y14_N8 2 " "Info: 2: + IC(3.207 ns) + CELL(0.542 ns) = 3.749 ns; Loc. = LC_X7_Y14_N8; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[9\]'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "3.749 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9] } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.542 ns 14.46 % " "Info: Total cell delay = 0.542 ns ( 14.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.207 ns 85.54 % " "Info: Total interconnect delay = 3.207 ns ( 85.54 % )" {  } {  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "3.749 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9] } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "3.749 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9] } { 0.000ns 3.207ns } { 0.000ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.542 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN ELA_X0_Y15_N0 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = ELA_X0_Y15_N0; Fanout = 23; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.223 ns) + CELL(0.319 ns) 1.542 ns sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[9\] 2 REG LC_X7_Y14_N8 2 " "Info: 2: + IC(1.223 ns) + CELL(0.319 ns) = 1.542 ns; Loc. = LC_X7_Y14_N8; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[9\]'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "1.542 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9] } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 1029 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.319 ns 20.69 % " "Info: Total cell delay = 0.319 ns ( 20.69 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.223 ns 79.31 % " "Info: Total interconnect delay = 1.223 ns ( 79.31 % )" {  } {  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "1.542 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9] } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "1.542 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9] } { 0.000ns 1.223ns } { 0.000ns 0.319ns } } }  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "3.749 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9] } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "3.749 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9] } { 0.000ns 3.207ns } { 0.000ns 0.542ns } } } { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "1.542 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9] } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "1.542 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[9] } { 0.000ns 1.223ns } { 0.000ns 0.319ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 25 23:47:54 2005 " "Info: Processing ended: Sun Dec 25 23:47:54 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}