lpm_rom0.tan.qmsg

s盒设计源程序 可以用语DES设计

{ "Info" "ITDB_TSU_RESULT" "altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_address_reg2 address\[2\] clock 3.244 ns memory " "Info: tsu for memory \"altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_address_reg2\" (data pin = \"address\[2\]\", clock pin = \"clock\") is 3.244 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.940 ns + Longest pin memory " "Info: + Longest pin to memory delay is 5.940 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns address\[2\] 1 PIN PIN_P14 1 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_P14; Fanout = 1; PIN Node = 'address\[2\]'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { address[2] } "NODE_NAME" } "" } } { "lpm_rom0.vhd" "" { Text "E:/weiling work/lpm/s_box/lpm_rom0.vhd" 48 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.253 ns) 5.940 ns altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_address_reg2 2 MEM M4K_X15_Y11 8 " "Info: 2: + IC(4.600 ns) + CELL(0.253 ns) = 5.940 ns; Loc. = M4K_X15_Y11; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_address_reg2'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "4.853 ns" { address[2] altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_address_reg2 } "NODE_NAME" } "" } } { "db/altsyncram_3s92.tdf" "" { Text "E:/weiling work/lpm/s_box/db/altsyncram_3s92.tdf" 290 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.340 ns 22.56 % " "Info: Total cell delay = 1.340 ns ( 22.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.600 ns 77.44 % " "Info: Total interconnect delay = 4.600 ns ( 77.44 % )" {  } {  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "5.940 ns" { address[2] altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_address_reg2 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "5.940 ns" { address[2] address[2]~out0 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_address_reg2 } { 0.000ns 0.000ns 4.600ns } { 0.000ns 1.087ns 0.253ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.131 ns + " "Info: + Micro setup delay of destination is 0.131 ns" {  } { { "db/altsyncram_3s92.tdf" "" { Text "E:/weiling work/lpm/s_box/db/altsyncram_3s92.tdf" 290 2 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.827 ns - Shortest memory " "Info: - Shortest clock path from clock \"clock\" to destination memory is 2.827 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clock 1 CLK PIN_L2 33 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 33; CLK Node = 'clock'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { clock } "NODE_NAME" } "" } } { "lpm_rom0.vhd" "" { Text "E:/weiling work/lpm/s_box/lpm_rom0.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.590 ns) + CELL(0.512 ns) 2.827 ns altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_address_reg2 2 MEM M4K_X15_Y11 8 " "Info: 2: + IC(1.590 ns) + CELL(0.512 ns) = 2.827 ns; Loc. = M4K_X15_Y11; Fanout = 8; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_address_reg2'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.102 ns" { clock altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_address_reg2 } "NODE_NAME" } "" } } { "db/altsyncram_3s92.tdf" "" { Text "E:/weiling work/lpm/s_box/db/altsyncram_3s92.tdf" 290 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.237 ns 43.76 % " "Info: Total cell delay = 1.237 ns ( 43.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.590 ns 56.24 % " "Info: Total interconnect delay = 1.590 ns ( 56.24 % )" {  } {  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.827 ns" { clock altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_address_reg2 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "2.827 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_address_reg2 } { 0.000ns 0.000ns 1.590ns } { 0.000ns 0.725ns 0.512ns } } }  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "5.940 ns" { address[2] altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_address_reg2 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "5.940 ns" { address[2] address[2]~out0 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_address_reg2 } { 0.000ns 0.000ns 4.600ns } { 0.000ns 1.087ns 0.253ns } } } { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.827 ns" { clock altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_address_reg2 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "2.827 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_address_reg2 } { 0.000ns 0.000ns 1.590ns } { 0.000ns 0.725ns 0.512ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clock q\[4\] altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|q_a\[4\] 7.990 ns memory " "Info: tco from clock \"clock\" to destination pin \"q\[4\]\" through memory \"altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|q_a\[4\]\" is 7.990 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.815 ns + Longest memory " "Info: + Longest clock path from clock \"clock\" to source memory is 2.815 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clock 1 CLK PIN_L2 33 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 33; CLK Node = 'clock'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { clock } "NODE_NAME" } "" } } { "lpm_rom0.vhd" "" { Text "E:/weiling work/lpm/s_box/lpm_rom0.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.590 ns) + CELL(0.500 ns) 2.815 ns altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|q_a\[4\] 2 MEM M4K_X15_Y11 1 " "Info: 2: + IC(1.590 ns) + CELL(0.500 ns) = 2.815 ns; Loc. = M4K_X15_Y11; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|q_a\[4\]'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.090 ns" { clock altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[4] } "NODE_NAME" } "" } } { "db/altsyncram_3s92.tdf" "" { Text "E:/weiling work/lpm/s_box/db/altsyncram_3s92.tdf" 47 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.225 ns 43.52 % " "Info: Total cell delay = 1.225 ns ( 43.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.590 ns 56.48 % " "Info: Total interconnect delay = 1.590 ns ( 56.48 % )" {  } {  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.815 ns" { clock altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[4] } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "2.815 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[4] } { 0.000ns 0.000ns 1.590ns } { 0.000ns 0.725ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.420 ns + " "Info: + Micro clock to output delay of source is 0.420 ns" {  } { { "db/altsyncram_3s92.tdf" "" { Text "E:/weiling work/lpm/s_box/db/altsyncram_3s92.tdf" 47 2 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.755 ns + Longest memory pin " "Info: + Longest memory to pin delay is 4.755 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.071 ns altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|q_a\[4\] 1 MEM M4K_X15_Y11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.071 ns) = 0.071 ns; Loc. = M4K_X15_Y11; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|q_a\[4\]'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[4] } "NODE_NAME" } "" } } { "db/altsyncram_3s92.tdf" "" { Text "E:/weiling work/lpm/s_box/db/altsyncram_3s92.tdf" 47 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.280 ns) + CELL(2.404 ns) 4.755 ns q\[4\] 2 PIN PIN_U15 0 " "Info: 2: + IC(2.280 ns) + CELL(2.404 ns) = 4.755 ns; Loc. = PIN_U15; Fanout = 0; PIN Node = 'q\[4\]'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "4.684 ns" { altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[4] q[4] } "NODE_NAME" } "" } } { "lpm_rom0.vhd" "" { Text "E:/weiling work/lpm/s_box/lpm_rom0.vhd" 50 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.475 ns 52.05 % " "Info: Total cell delay = 2.475 ns ( 52.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.280 ns 47.95 % " "Info: Total interconnect delay = 2.280 ns ( 47.95 % )" {  } {  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "4.755 ns" { altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[4] q[4] } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "4.755 ns" { altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[4] q[4] } { 0.000ns 2.280ns } { 0.071ns 2.404ns } } }  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.815 ns" { clock altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[4] } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "2.815 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[4] } { 0.000ns 0.000ns 1.590ns } { 0.000ns 0.725ns 0.500ns } } } { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "4.755 ns" { altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[4] q[4] } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "4.755 ns" { altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|q_a[4] q[4] } { 0.000ns 2.280ns } { 0.071ns 2.404ns } } }  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.404 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.404 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN ELA_X0_Y15_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = ELA_X0_Y15_N0; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.404 ns) 2.404 ns altera_reserved_tdo 2 PIN PIN_H11 0 " "Info: 2: + IC(0.000 ns) + CELL(2.404 ns) = 2.404 ns; Loc. = PIN_H11; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.404 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns 100.00 % " "Info: Total cell delay = 2.404 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.404 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "2.404 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 2.404ns } } }  } 0}