lpm_rom0.tan.qmsg

s盒设计源程序 可以用语DES设计

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "lpm_rom0.vhd" "" { Text "E:/weiling work/lpm/s_box/lpm_rom0.vhd" 49 -1 0 } } { "e:/quartus2/bin/Assignment Editor.qase" "" { Assignment "e:/quartus2/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "e:/quartus2/bin/Assignment Editor.qase" "" { Assignment "e:/quartus2/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock memory altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_datain_reg7 memory altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_memory_reg7 290.87 MHz 3.438 ns Internal " "Info: Clock \"clock\" has Internal fmax of 290.87 MHz between source memory \"altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_datain_reg7\" and destination memory \"altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_memory_reg7\" (period= 3.438 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.875 ns + Longest memory memory " "Info: + Longest memory to memory delay is 2.875 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_datain_reg7 1 MEM M4K_X15_Y11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X15_Y11; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_datain_reg7'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_3s92.tdf" "" { Text "E:/weiling work/lpm/s_box/db/altsyncram_3s92.tdf" 290 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.875 ns) 2.875 ns altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_memory_reg7 2 MEM M4K_X15_Y11 0 " "Info: 2: + IC(0.000 ns) + CELL(2.875 ns) = 2.875 ns; Loc. = M4K_X15_Y11; Fanout = 0; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_memory_reg7'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.875 ns" { altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_datain_reg7 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_3s92.tdf" "" { Text "E:/weiling work/lpm/s_box/db/altsyncram_3s92.tdf" 290 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.875 ns 100.00 % " "Info: Total cell delay = 2.875 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.875 ns" { altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_datain_reg7 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "2.875 ns" { altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_datain_reg7 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_memory_reg7 } { 0.000ns 0.000ns } { 0.000ns 2.875ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.012 ns - Smallest " "Info: - Smallest clock skew is -0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.815 ns + Shortest memory " "Info: + Shortest clock path from clock \"clock\" to destination memory is 2.815 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clock 1 CLK PIN_L2 33 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 33; CLK Node = 'clock'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { clock } "NODE_NAME" } "" } } { "lpm_rom0.vhd" "" { Text "E:/weiling work/lpm/s_box/lpm_rom0.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.590 ns) + CELL(0.500 ns) 2.815 ns altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_memory_reg7 2 MEM M4K_X15_Y11 0 " "Info: 2: + IC(1.590 ns) + CELL(0.500 ns) = 2.815 ns; Loc. = M4K_X15_Y11; Fanout = 0; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_memory_reg7'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.090 ns" { clock altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_3s92.tdf" "" { Text "E:/weiling work/lpm/s_box/db/altsyncram_3s92.tdf" 290 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.225 ns 43.52 % " "Info: Total cell delay = 1.225 ns ( 43.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.590 ns 56.48 % " "Info: Total interconnect delay = 1.590 ns ( 56.48 % )" {  } {  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.815 ns" { clock altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "2.815 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_memory_reg7 } { 0.000ns 0.000ns 1.590ns } { 0.000ns 0.725ns 0.500ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.827 ns - Longest memory " "Info: - Longest clock path from clock \"clock\" to source memory is 2.827 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clock 1 CLK PIN_L2 33 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 33; CLK Node = 'clock'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { clock } "NODE_NAME" } "" } } { "lpm_rom0.vhd" "" { Text "E:/weiling work/lpm/s_box/lpm_rom0.vhd" 49 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.590 ns) + CELL(0.512 ns) 2.827 ns altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_datain_reg7 2 MEM M4K_X15_Y11 1 " "Info: 2: + IC(1.590 ns) + CELL(0.512 ns) = 2.827 ns; Loc. = M4K_X15_Y11; Fanout = 1; MEM Node = 'altsyncram:altsyncram_component\|altsyncram_95s:auto_generated\|altsyncram_3s92:altsyncram1\|ram_block3a7~porta_datain_reg7'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.102 ns" { clock altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } "" } } { "db/altsyncram_3s92.tdf" "" { Text "E:/weiling work/lpm/s_box/db/altsyncram_3s92.tdf" 290 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.237 ns 43.76 % " "Info: Total cell delay = 1.237 ns ( 43.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.590 ns 56.24 % " "Info: Total interconnect delay = 1.590 ns ( 56.24 % )" {  } {  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.827 ns" { clock altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "2.827 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_datain_reg7 } { 0.000ns 0.000ns 1.590ns } { 0.000ns 0.725ns 0.512ns } } }  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.815 ns" { clock altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "2.815 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_memory_reg7 } { 0.000ns 0.000ns 1.590ns } { 0.000ns 0.725ns 0.500ns } } } { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.827 ns" { clock altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "2.827 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_datain_reg7 } { 0.000ns 0.000ns 1.590ns } { 0.000ns 0.725ns 0.512ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.420 ns + " "Info: + Micro clock to output delay of source is 0.420 ns" {  } { { "db/altsyncram_3s92.tdf" "" { Text "E:/weiling work/lpm/s_box/db/altsyncram_3s92.tdf" 290 2 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.131 ns + " "Info: + Micro setup delay of destination is 0.131 ns" {  } { { "db/altsyncram_3s92.tdf" "" { Text "E:/weiling work/lpm/s_box/db/altsyncram_3s92.tdf" 290 2 0 } }  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.875 ns" { altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_datain_reg7 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "2.875 ns" { altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_datain_reg7 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_memory_reg7 } { 0.000ns 0.000ns } { 0.000ns 2.875ns } } } { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.815 ns" { clock altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_memory_reg7 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "2.815 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_memory_reg7 } { 0.000ns 0.000ns 1.590ns } { 0.000ns 0.725ns 0.500ns } } } { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.827 ns" { clock altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_datain_reg7 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "2.827 ns" { clock clock~out0 altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1|ram_block3a7~porta_datain_reg7 } { 0.000ns 0.000ns 1.590ns } { 0.000ns 0.725ns 0.512ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|HUB_BYPASS_REG register sld_hub:sld_hub_inst\|HUB_TDO~reg0 175.99 MHz 5.682 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 175.99 MHz between source register \"sld_hub:sld_hub_inst\|HUB_BYPASS_REG\" and destination register \"sld_hub:sld_hub_inst\|HUB_TDO~reg0\" (period= 5.682 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.667 ns + Longest register register " "Info: + Longest register to register delay is 2.667 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|HUB_BYPASS_REG 1 REG LC_X5_Y12_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y12_N2; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|HUB_BYPASS_REG'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { sld_hub:sld_hub_inst|HUB_BYPASS_REG } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 912 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.986 ns) + CELL(0.366 ns) 1.352 ns sld_hub:sld_hub_inst\|HUB_TDO~350 2 COMB LC_X6_Y11_N1 1 " "Info: 2: + IC(0.986 ns) + CELL(0.366 ns) = 1.352 ns; Loc. = LC_X6_Y11_N1; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|HUB_TDO~350'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "1.352 ns" { sld_hub:sld_hub_inst|HUB_BYPASS_REG sld_hub:sld_hub_inst|HUB_TDO~350 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 134 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.776 ns) + CELL(0.539 ns) 2.667 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 3 REG LC_X9_Y11_N1 0 " "Info: 3: + IC(0.776 ns) + CELL(0.539 ns) = 2.667 ns; Loc. = LC_X9_Y11_N1; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "1.315 ns" { sld_hub:sld_hub_inst|HUB_TDO~350 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.905 ns 33.93 % " "Info: Total cell delay = 0.905 ns ( 33.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.762 ns 66.07 % " "Info: Total interconnect delay = 1.762 ns ( 66.07 % )" {  } {  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.667 ns" { sld_hub:sld_hub_inst|HUB_BYPASS_REG sld_hub:sld_hub_inst|HUB_TDO~350 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "2.667 ns" { sld_hub:sld_hub_inst|HUB_BYPASS_REG sld_hub:sld_hub_inst|HUB_TDO~350 sld_hub:sld_hub_inst|HUB_TDO~reg0 } { 0.000ns 0.986ns 0.776ns } { 0.000ns 0.366ns 0.539ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.008 ns - Smallest " "Info: - Smallest clock skew is -0.008 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 3.726 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 3.726 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK ELA_X0_Y15_N0 128 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = ELA_X0_Y15_N0; Fanout = 128; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.184 ns) + CELL(0.542 ns) 3.726 ns sld_hub:sld_hub_inst\|HUB_TDO~reg0 2 REG LC_X9_Y11_N1 0 " "Info: 2: + IC(3.184 ns) + CELL(0.542 ns) = 3.726 ns; Loc. = LC_X9_Y11_N1; Fanout = 0; REG Node = 'sld_hub:sld_hub_inst\|HUB_TDO~reg0'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "3.726 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.542 ns 14.55 % " "Info: Total cell delay = 0.542 ns ( 14.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.184 ns 85.45 % " "Info: Total interconnect delay = 3.184 ns ( 85.45 % )" {  } {  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "3.726 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "3.726 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } { 0.000ns 3.184ns } { 0.000ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 3.734 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 3.734 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK ELA_X0_Y15_N0 128 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = ELA_X0_Y15_N0; Fanout = 128; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.192 ns) + CELL(0.542 ns) 3.734 ns sld_hub:sld_hub_inst\|HUB_BYPASS_REG 2 REG LC_X5_Y12_N2 1 " "Info: 2: + IC(3.192 ns) + CELL(0.542 ns) = 3.734 ns; Loc. = LC_X5_Y12_N2; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|HUB_BYPASS_REG'" {  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "3.734 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_BYPASS_REG } "NODE_NAME" } "" } } { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 912 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.542 ns 14.52 % " "Info: Total cell delay = 0.542 ns ( 14.52 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.192 ns 85.48 % " "Info: Total interconnect delay = 3.192 ns ( 85.48 % )" {  } {  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "3.734 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_BYPASS_REG } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "3.734 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_BYPASS_REG } { 0.000ns 3.192ns } { 0.000ns 0.542ns } } }  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "3.726 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "3.726 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } { 0.000ns 3.184ns } { 0.000ns 0.542ns } } } { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "3.734 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_BYPASS_REG } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "3.734 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_BYPASS_REG } { 0.000ns 3.192ns } { 0.000ns 0.542ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 912 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 912 -1 0 } } { "sld_hub.vhd" "" { Text "e:/quartus2/libraries/megafunctions/sld_hub.vhd" 937 -1 0 } }  } 0}  } { { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "2.667 ns" { sld_hub:sld_hub_inst|HUB_BYPASS_REG sld_hub:sld_hub_inst|HUB_TDO~350 sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "2.667 ns" { sld_hub:sld_hub_inst|HUB_BYPASS_REG sld_hub:sld_hub_inst|HUB_TDO~350 sld_hub:sld_hub_inst|HUB_TDO~reg0 } { 0.000ns 0.986ns 0.776ns } { 0.000ns 0.366ns 0.539ns } } } { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "3.726 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "3.726 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_TDO~reg0 } { 0.000ns 3.184ns } { 0.000ns 0.542ns } } } { "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" "" { Report "E:/weiling work/lpm/s_box/db/lpm_rom0_cmp.qrpt" Compiler "lpm_rom0" "UNKNOWN" "V1" "E:/weiling work/lpm/s_box/db/lpm_rom0.quartus_db" { Floorplan "E:/weiling work/lpm/s_box/" "" "3.734 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_BYPASS_REG } "NODE_NAME" } "" } } { "e:/quartus2/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/quartus2/bin/Technology_Viewer.qrui" "3.734 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|HUB_BYPASS_REG } { 0.000ns 3.192ns } { 0.000ns 0.542ns } } }  } 0}