📄 lpm_rom0.map.rpt
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; 2:1 ; 5 bits ; 5 LEs ; 5 LEs ; 0 LEs ; Yes ; |lpm_rom0|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[4] ;
; 2:1 ; 5 bits ; 5 LEs ; 5 LEs ; 0 LEs ; Yes ; |lpm_rom0|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[4] ;
; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |lpm_rom0|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[1] ;
; 18:1 ; 4 bits ; 48 LEs ; 28 LEs ; 20 LEs ; Yes ; |lpm_rom0|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[1] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+--------------------------------------------------------+-------+
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 32 ;
; Number of synthesis-generated cells ; 128 ;
; Number of WYSIWYG LUTs ; 32 ;
; Number of synthesis-generated LUTs ; 97 ;
; Number of WYSIWYG registers ; 27 ;
; Number of synthesis-generated registers ; 76 ;
; Number of cells with combinational logic only ; 57 ;
; Number of cells with registers only ; 31 ;
; Number of cells with combinational logic and registers ; 72 ;
+--------------------------------------------------------+-------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 103 ;
; Number of registers using Synchronous Clear ; 15 ;
; Number of registers using Synchronous Load ; 12 ;
; Number of registers using Asynchronous Clear ; 73 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 69 ;
; Number of registers using Output Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; sld_hub:sld_hub_inst|HUB_TDO~reg0 ; 1 ;
; Total number of inverted registers = 1 ; ;
+----------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------------------------------+
; In-System Memory Content Editor Settings ;
+----------------+-------------+-------+-------+------------+-------------------------------------------------------------------------+
; Instance Index ; Instance ID ; Width ; Depth ; Mode ; Hierarchy Location ;
+----------------+-------------+-------+-------+------------+-------------------------------------------------------------------------+
; 0 ; NONE ; 8 ; 256 ; Read/Write ; |lpm_rom0|altsyncram:altsyncram_component|altsyncram_95s:auto_generated ;
+----------------+-------------+-------+-------+------------+-------------------------------------------------------------------------+
+-----------+
; Hierarchy ;
+-----------+
lpm_rom0
|-- altsyncram:altsyncram_component
|-- altsyncram_95s:auto_generated
|-- altsyncram_3s92:altsyncram1
|-- sld_mod_ram_rom:mgl_prim2
|-- sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr
|-- lpm_counter:ram_rom_addr_reg_rtl_0
|-- cntr_ov8:auto_generated
|-- lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1
|-- cntr_re8:auto_generated
|-- sld_hub:sld_hub_inst
|-- sld_dffex:\GEN_IRF:1:IRF
|-- sld_dffex:\GEN_SHADOW_IRF:1:S_IRF
|-- sld_dffex:BROADCAST
|-- sld_rom_sr:HUB_INFO_REG
|-- lpm_decode:instruction_decoder
|-- decode_bje:auto_generated
|-- sld_dffex:IRF_ENA
|-- sld_dffex:IRF_ENA_0
|-- sld_dffex:IRSR
|-- lpm_shiftreg:jtag_ir_register
|-- sld_jtag_state_machine:jtag_state_machine
|-- sld_dffex:RESET
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+---------------------------------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; |lpm_rom0 ; 160 (1) ; 103 ; 2048 ; 0 ; 0 ; 0 ; 0 ; 17 ; 0 ; 57 (1) ; 31 (0) ; 72 (0) ; 17 (0) ; |lpm_rom0 ;
; |altsyncram:altsyncram_component| ; 53 (0) ; 34 ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (0) ; 7 (0) ; 27 (0) ; 12 (0) ; |lpm_rom0|altsyncram:altsyncram_component ;
; |altsyncram_95s:auto_generated| ; 53 (0) ; 34 ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (0) ; 7 (0) ; 27 (0) ; 12 (0) ; |lpm_rom0|altsyncram:altsyncram_component|altsyncram_95s:auto_generated ;
; |altsyncram_3s92:altsyncram1| ; 0 (0) ; 0 ; 2048 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |lpm_rom0|altsyncram:altsyncram_component|altsyncram_95s:auto_generated|altsyncram_3s92:altsyncram1 ;
; |sld_mod_ram_rom:mgl_prim2| ; 53 (26) ; 34 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (12) ; 7 (5) ; 27 (9) ; 12 (0) ; |lpm_rom0|altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2 ;
; |lpm_counter:ram_rom_addr_reg_rtl_0| ; 8 (0) ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (0) ; 8 (0) ; |lpm_rom0|altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0 ;
; |cntr_ov8:auto_generated| ; 8 (8) ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; 8 (8) ; |lpm_rom0|altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_ov8:auto_generated ;
; |lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1| ; 4 (0) ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; |lpm_rom0|altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1 ;
; |cntr_re8:auto_generated| ; 4 (4) ; 4 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; |lpm_rom0|altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_re8:auto_generated ;
; |sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr| ; 15 (15) ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 2 (2) ; 6 (6) ; 0 (0) ; |lpm_rom0|altsyncram:altsyncram_component|altsyncram_95s:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr ;
; |sld_hub:sld_hub_inst| ; 106 (29) ; 69 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 37 (23) ; 24 (1) ; 45 (5) ; 5 (0) ; |lpm_rom0|sld_hub:sld_hub_inst ;
; |lpm_decode:instruction_decoder| ; 5 (0) ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (0) ; 0 (0) ; |lpm_rom0|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder ;
; |decode_bje:auto_generated| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; |lpm_rom0|sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_bje:auto_generated ;
; |lpm_shiftreg:jtag_ir_register| ; 10 (10) ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 10 (10) ; 0 (0) ; 0 (0) ; |lpm_rom0|sld_hub:sld_hub_inst|lpm_shiftreg:jtag_ir_register ;
; |sld_dffex:BROADCAST| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |lpm_rom0|sld_hub:sld_hub_inst|sld_dffex:BROADCAST ;
; |sld_dffex:IRF_ENA_0| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |lpm_rom0|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0 ;
; |sld_dffex:IRF_ENA| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |lpm_rom0|sld_hub:sld_hub_inst|sld_dffex:IRF_ENA ;
; |sld_dffex:IRSR| ; 8 (8) ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 1 (1) ; 5 (5) ; 0 (0) ; |lpm_rom0|sld_hub:sld_hub_inst|sld_dffex:IRSR ;
; |sld_dffex:RESET| ; 1 (1) ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |lpm_rom0|sld_hub:sld_hub_inst|sld_dffex:RESET ;
; |sld_dffex:\GEN_IRF:1:IRF| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 0 (0) ; |lpm_rom0|sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF ;
; |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 5 (5) ; 0 (0) ; 0 (0) ; |lpm_rom0|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF ;
; |sld_jtag_state_machine:jtag_state_machine| ; 20 (20) ; 19 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 19 (19) ; 0 (0) ; |lpm_rom0|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine ;
; |sld_rom_sr:HUB_INFO_REG| ; 20 (20) ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 11 (11) ; 3 (3) ; 6 (6) ; 5 (5) ; |lpm_rom0|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ;
+---------------------------------------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/weiling work/lpm/s_box/lpm_rom0.map.eqn.
+------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path ;
+----------------------------------+-----------------+-------------------------------------------------------------+
; lpm_rom0.vhd ; yes ; E:/weiling work/lpm/s_box/lpm_rom0.vhd ;
; altsyncram.tdf ; yes ; e:/quartus2/libraries/megafunctions/altsyncram.tdf ;
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