hal_regs.h

epson公司的一个关于s1d13706的低层驱动程序

/*===========================================================================
**  HAL_REGS.H 
**---------------------------------------------------------------------------
** Copyright (c) 2000, 2001 Epson Research and Development, Inc.
** All Rights Reserved.
===========================================================================*/

#ifndef __HAL_REGS_H__
#define __HAL_REGS_H__

/*
** 13706 register names
*/

#define REG_REVISION_CODE              0x00
#define REG_DISP_BUFFER_SIZE           0x01
#define REG_CONFIG_READBACK            0x02
#define REG_BUSCLK_MEMCLK_CONFIG       0x04
#define REG_PCLK_CONFIG                0x05
#define REG_LUT_BLUE_WRITE_DATA        0x08
#define REG_LUT_GREEN_WRITE_DATA       0x09
#define REG_LUT_RED_WRITE_DATA         0x0a
#define REG_LUT_WRITE_ADDR             0x0b
#define REG_LUT_BLUE_READ_DATA         0x0c
#define REG_LUT_GREEN_READ_DATA        0x0d
#define REG_LUT_RED_READ_DATA          0x0e
#define REG_LUT_READ_ADDR              0x0f
#define REG_PANEL_TYPE                 0x10
#define REG_MOD_RATE                   0x11
#define REG_HORIZ_TOTAL                0x12
#define REG_HDP                        0x14
#define REG_HDP_START_POS0             0x16
#define REG_HDP_START_POS1             0x17
#define REG_VERT_TOTAL0                0x18
#define REG_VERT_TOTAL1                0x19
#define REG_VDP0                       0x1c
#define REG_VDP1                       0x1d
#define REG_VDP_START_POS0             0x1e
#define REG_VDP_START_POS1             0x1f
#define REG_HSYNC_PULSE_WIDTH          0x20
#define REG_HSYNC_PULSE_START_POS0     0x22
#define REG_HSYNC_PULSE_START_POS1     0x23
#define REG_VSYNC_PULSE_WIDTH          0x24
#define REG_VSYNC_PULSE_START_POS0     0x26
#define REG_VSYNC_PULSE_START_POS1     0x27 
#define REG_DTFD_GCP_INDEX             0x28
#define REG_DTFD_GCP_DATA              0x2c
#define REG_DISPLAY_MODE               0x70
#define REG_SPECIAL_EFFECTS            0x71
#define REG_MAIN_WIN_DISP_START_ADDR0  0x74
#define REG_MAIN_WIN_DISP_START_ADDR1  0x75
#define REG_MAIN_WIN_DISP_START_ADDR2  0x76
#define REG_MAIN_WIN_ADDR_OFFSET0      0x78
#define REG_MAIN_WIN_ADDR_OFFSET1      0x79
#define REG_SUB_WIN_DISP_START_ADDR0   0x7c
#define REG_SUB_WIN_DISP_START_ADDR1   0x7d
#define REG_SUB_WIN_DISP_START_ADDR2   0x7e
#define REG_SUB_WIN_ADDR_OFFSET0       0x80
#define REG_SUB_WIN_ADDR_OFFSET1       0x81
#define REG_SUB_WIN_X_START_POS0       0x84
#define REG_SUB_WIN_X_START_POS1       0x85
#define REG_SUB_WIN_Y_START_POS0       0x88
#define REG_SUB_WIN_Y_START_POS1       0x89
#define REG_SUB_WIN_X_END_POS0         0x8c
#define REG_SUB_WIN_X_END_POS1         0x8d
#define REG_SUB_WIN_Y_END_POS0         0x90
#define REG_SUB_WIN_Y_END_POS1         0x91
#define REG_POWER_SAVE_CONFIG          0xa0
#define REG_CPU_ACCESS_CONTROL         0xa1
#define REG_SOFTWARE_RESET             0xa2
#define REG_BIG_ENDIAN_SUPPORT         0xa3
#define REG_SCRATCH_PAD0               0xa4
#define REG_SCRATCH_PAD1               0xa5
#define REG_GPIO_CONFIG0               0xa8
#define REG_GPIO_CONFIG1               0xa9
#define REG_GPIO_STATUS_CONTROL0       0xac
#define REG_GPIO_STATUS_CONTROL1       0xad
#define REG_PWM_CV_CLOCK_CONTROL       0xb0
#define REG_PWM_CV_CLOCK_CONFIG        0xb1
#define REG_CV_CLOCK_BURST_LENGTH      0xb2
#define REG_PWM_CLOCK_DUTY_CYCLE       0xb3


/*
** In total, there are 67 bytes of registers.
** For initialization, reserve 100 bytes for registers.
*/
#define MAX_REG    100


/*
** Highest reg is the highest register address.
*/
#define HIGHEST_REG    REG_PWM_CLOCK_DUTY_CYCLE


/*
** Indicate that register definitions are finished in appcfg.h
*/
#define FINISHED_REG_CFG    0xffff


#endif      /*  __HAL_REGS_H__ */