appcfg.h

epson公司的一个关于s1d13706的低层驱动程序

/******************************************************************************/
/*                                                                            */
/*  HAL_STRUCT Information generated by 13706CFG.EXE                          */
/*                                                                            */
/*  Copyright (c) 2000, 2001 Epson Research and Development, Inc.             */
/*  All rights reserved.                                                      */
/*                                                                            */
/*  Panel: 320x240x8bpp 70Hz Color Single STN 4-bit (PCLK=6.250MHz)*/
/*                                                                            */
/*  Include this file ONCE in your primary source file.                       */
/*  Set compiler options to pack the structure on a byte boundary.            */
/*                                                                            */
/******************************************************************************/

HAL_STRUCT HalInfo = 
    {
    "1376 HAL EXE",     /* ID string */
    0x1234,             /* Detect Endian */
    sizeof(HAL_STRUCT), /* Size */
    0 | fVALID_LCD,    /* Flags */
        {
        /* Registers */
        {REG_BUSCLK_MEMCLK_CONFIG      ,0x00},   /* Reg    4h */
        {REG_PCLK_CONFIG               ,0x43},   /* Reg    5h */
        {REG_PANEL_TYPE                ,0x40},   /* Reg   10h */
        {REG_MOD_RATE                  ,0x00},   /* Reg   11h */
        {REG_HORIZ_TOTAL               ,0x2b},   /* Reg   12h */
        {REG_HDP                       ,0x27},   /* Reg   14h */
        {REG_HDP_START_POS0            ,0x00},   /* Reg   16h */
        {REG_HDP_START_POS1            ,0x00},   /* Reg   17h */
        {REG_VERT_TOTAL0               ,0xfa},   /* Reg   18h */
        {REG_VERT_TOTAL1               ,0x00},   /* Reg   19h */
        {REG_VDP0                      ,0xef},   /* Reg   1ch */
        {REG_VDP1                      ,0x00},   /* Reg   1dh */
        {REG_VDP_START_POS0            ,0x00},   /* Reg   1eh */
        {REG_VDP_START_POS1            ,0x00},   /* Reg   1fh */
        {REG_HSYNC_PULSE_WIDTH         ,0x87},   /* Reg   20h */
        {REG_HSYNC_PULSE_START_POS0    ,0x00},   /* Reg   22h */
        {REG_HSYNC_PULSE_START_POS1    ,0x00},   /* Reg   23h */
        {REG_VSYNC_PULSE_WIDTH         ,0x80},   /* Reg   24h */
        {REG_VSYNC_PULSE_START_POS0    ,0x00},   /* Reg   26h */
        {REG_VSYNC_PULSE_START_POS1    ,0x00},   /* Reg   27h */
        {REG_DISPLAY_MODE              ,0x03},   /* Reg   70h */
        {REG_SPECIAL_EFFECTS           ,0x00},   /* Reg   71h */
        {REG_MAIN_WIN_DISP_START_ADDR0 ,0x00},   /* Reg   74h */
        {REG_MAIN_WIN_DISP_START_ADDR1 ,0x00},   /* Reg   75h */
        {REG_MAIN_WIN_DISP_START_ADDR2 ,0x00},   /* Reg   76h */
        {REG_MAIN_WIN_ADDR_OFFSET0     ,0x50},   /* Reg   78h */
        {REG_MAIN_WIN_ADDR_OFFSET1     ,0x00},   /* Reg   79h */
        {REG_SUB_WIN_DISP_START_ADDR0  ,0x00},   /* Reg   7ch */
        {REG_SUB_WIN_DISP_START_ADDR1  ,0x00},   /* Reg   7dh */
        {REG_SUB_WIN_DISP_START_ADDR2  ,0x00},   /* Reg   7eh */
        {REG_SUB_WIN_ADDR_OFFSET0      ,0x50},   /* Reg   80h */
        {REG_SUB_WIN_ADDR_OFFSET1      ,0x00},   /* Reg   81h */
        {REG_SUB_WIN_X_START_POS0      ,0x00},   /* Reg   84h */
        {REG_SUB_WIN_X_START_POS1      ,0x00},   /* Reg   85h */
        {REG_SUB_WIN_Y_START_POS0      ,0x00},   /* Reg   88h */
        {REG_SUB_WIN_Y_START_POS1      ,0x00},   /* Reg   89h */
        {REG_SUB_WIN_X_END_POS0        ,0x4f},   /* Reg   8ch */
        {REG_SUB_WIN_X_END_POS1        ,0x00},   /* Reg   8dh */
        {REG_SUB_WIN_Y_END_POS0        ,0xef},   /* Reg   90h */
        {REG_SUB_WIN_Y_END_POS1        ,0x00},   /* Reg   91h */
        {REG_POWER_SAVE_CONFIG         ,0x00},   /* Reg   a0h */
        {REG_CPU_ACCESS_CONTROL        ,0x00},   /* Reg   a1h */
        {REG_SOFTWARE_RESET            ,0x00},   /* Reg   a2h */
        {REG_BIG_ENDIAN_SUPPORT        ,0x00},   /* Reg   a3h */
        {REG_SCRATCH_PAD0              ,0x00},   /* Reg   a4h */
        {REG_SCRATCH_PAD1              ,0x00},   /* Reg   a5h */
        {REG_GPIO_CONFIG0              ,0x00},   /* Reg   a8h */
        {REG_GPIO_CONFIG1              ,0x00},   /* Reg   a9h */
        {REG_GPIO_STATUS_CONTROL0      ,0x00},   /* Reg   ach */
        {REG_GPIO_STATUS_CONTROL1      ,0x00},   /* Reg   adh */
        {REG_PWM_CV_CLOCK_CONTROL      ,0x00},   /* Reg   b0h */
        {REG_PWM_CV_CLOCK_CONFIG       ,0x00},   /* Reg   b1h */
        {REG_CV_CLOCK_BURST_LENGTH     ,0x00},   /* Reg   b2h */
        {REG_PWM_CLOCK_DUTY_CYCLE      ,0x00},   /* Reg   b3h */
        {FINISHED_REG_CFG,              0x00}
        },

    {
    /*GcpData*/
    0x52, 0xaa, 0x92, 0x22, 0x48, 0x88, 0x91, 0x22,
    0x49, 0x24, 0x92, 0x49, 0x49, 0x4a, 0x52, 0xa5,
    0x2a, 0x52, 0x49, 0x24, 0x48, 0x84, 0x20, 0x40,
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
    },

    50000,             /* ClkI (kHz)      */
    50000,             /* ClkI2 (kHz)     */

#ifdef INTEL_DOS
    8000,              /* Bus Clock (kHz) */
#else
    50000,             /* Bus Clock (kHz) */
#endif

#ifdef INTEL_DOS
    0x00e00000,        /* Registers      */
    0x00c00000,        /* Display Memory */
#elif defined(IDP68K)
    0x00F80000,        /* Registers      */
    0x00F00000,        /* Display Memory */
#elif defined(LCEVBSH3)
    0x14000000,        /* Registers      */
    0x04000000,        /* Display Memory */
#elif defined(DSP56654ADM)
    0x41000000,        /* Registers      */
    0x41020000,        /* Display Memory */
#else
    0x00000000,        /* Registers      */
    0x00000000,        /* Display Memory */
#endif

    70,                /* Panel Frame Rate (Hz)    */
    1200,              /* Time before LCD power off (in milliseconds) */
    50,                /* Time before LCD power on (in milliseconds) */
    0,                 /* Reserved                 */
    0,                 /* Reserved                 */
    0                  /* Reserved                 */
    };