cpu.c

IAR编译环境下的AT91SAM7S64芯片的ucosii系统移植和演示代码。

/*
*********************************************************************************************************
*                                            Atmel AT91 SAM7
*                                          CPU Specific Code
*
*                              (c) Copyright 2004, Micrium, Inc., Weston, FL
*                                          All Rights Reserved
*
*
* File : cpu.c
* By   : Eric Shufro
*********************************************************************************************************
*/

#include <includes.h>

/*
*********************************************************************************************************
*                                              CONSTANTS
*********************************************************************************************************
*/

#define  BSP_RAM_REMAP_TEST_BYTE             (*(INT8U  *)0x00000030L)

/*
*********************************************************************************************************
*                                               DATA TYPES
*********************************************************************************************************
*/

/*
*********************************************************************************************************
*                                              PROTOTYPES
*********************************************************************************************************
*/

/*
*********************************************************************************************************
*                                              CPU_Init
*
* Description:  Initialize the number of Flash wait states and setup the on-chip PLL
*********************************************************************************************************
*/

void CPU_Init(void)
{

   AT91PS_PMC     pPMC = AT91C_BASE_PMC;

   AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(50 <<16)) | AT91C_MC_FWS_1FWS ;    /* Set Flash Waite state.	                       */
                                                                                /* Single Cycle Access at Up to 30 MHz, or 40          */
                                                                                /* if MCK = 47923200 then there are 50 cycles for 1 uS */

   AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;                                /* Disable the Watchdog                                */

   pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));   /* Set MCK at 47 923 200                               */
                                                                                /* 1 Enabling the Main Oscillator:                     */
                                                                                /* SCK = 1/32768 = 30.51 uS                            */
                                                                                /* Start up time = 8 * 6 / SCK = 56 * 30.51 =          */
                                                                                /* 1,46484375 ms                                       */

   while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS))                                     /* Wait the startup time                               */
   {
      ;
   }
                                                                                /* Checking the Main Oscillator Frequency (Optional)   */
                                                                                /* Setup the PLL and divider:                          */
                                                                                /* - div by 5 Fin = 3,6864 =(18,432 / 5)               */
                                                                                /* - Mul 25+1: Fout =	95,8464 =(3,6864 *26)          */
                                                                                /* for 96 MHz the erroe is 0.16%                       */
                                                                                /* Field out NOT USED = 0                              */
                                                                                /* PLLCOUNT pll startup time esrtimate at : 0.844 ms   */
                                                                                /* PLLCOUNT 28 = 0.000844 /(1/32768)                   */

   pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | (AT91C_CKGR_PLLCOUNT & (28<<8)) | (AT91C_CKGR_MUL & (25<<16)));


   while(!(pPMC->PMC_SR & AT91C_PMC_LOCK))                                      /* Wait the startup time                               */
   {
       ;
   }

   pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2 ;     	        /* Selection of Master Clock and Processor Clock       */
                                                                                /* Select the PLL clock divided by 2                   */

   AT91C_BASE_MC->MC_RCR             =  1;                                      /* Toggle REMAP register                               */
   BSP_RAM_REMAP_TEST_BYTE           =  0x01;                                   /* Write a byte to RAM                                 */

   if(BSP_RAM_REMAP_TEST_BYTE       !=  0x01)                                   /* Check if the write to RAM worked                    */
      AT91C_BASE_MC->MC_RCR          =  1;                                      /* If not, toggle REMAP register                       */
}