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📄 aci31_x1.asm

📁 本程序来自TI公司网站原程序,其功能是通过传统的V/F控制算法来实现对感应电机的控制,控制程序可以采用.asm也可以采用.C。 程序的具体算法和介绍在软件压缩包有详细介绍!
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;=========================================================================================
; System Name:	ACI3_1
;
; File Name:	ACI31_x1.ASM 
;
; Description:	ACI 3-phase Volts / Hertz (VHz) control with speed
;			sensor		
;
; Originator:	Digital Control Systems Group
;			Texas Instruments
;
; Target Device:F240, F243, F2407
; To Select the target device see x24x_app.h file.
;
;							
;=====================================================================================
; History:
;-------------------------------------------------------------------------------------
; 9-15-2000	Release	Rev 1.0
;==============================================================================

;******************************************************************************
;					  SYSTEM OPTIONS
;******************************************************************************
real_time	        .set	1      ; 1 for real time mode, otherwise set 0
;******************************************************************************
phase1_commissioning	.set	1	;Check interrupts, DAC outputs and a few
					;target/system independent s/w modules.
phase2_commissioning	.set	0   	;Open loop V/Hz control		
phase3_commissioning	.set	0   	;Closed loop PID controller need to be 
					;optimized 
;-----------------------------------------------------------------------------
; External references
;-----------------------------------------------------------------------------
		.include	"x24x_app.h"
		.global MON_RT_CNFG

		.ref	SYS_INIT

		.ref	RAMP_CNTL, RAMP_CNTL_INIT			;function call
		.ref	target_value 					;Inputs
		.ref	setpt_value, s_eq_t_flg				;Outputs

		.ref	D_PID_REG, D_PID_REG_INIT			;function call
		.ref	D_fb, D_ref							;Inputs
		.ref	D_out								;Outputs

		.ref	V_Hz_PROFILE, V_Hz_PROFILE_INIT		;function call
		.ref	vhz_freq							;Inputs
		.ref	v_out								;Outputs

		.ref	SVGEN_MF, SVGEN_MF_INIT				;function call
		.ref	sv_gain, sv_offset, sv_freq			;Inputs
		.ref	Ta, Tb, Tc							;Outputs

		.ref	SPEED_PRD, SPEED_PRD_INIT			;function call
		.ref	time_stamp							;Inputs
		.ref	speed_prd, speed_rpm

		.ref	CAP_EVENT_DRV, CAP_EVENT_DRV_INIT		;function call

		.ref	FC_PWM_O_DRV
		.ref	FC_PWM_O_DRV_INIT						;function call
		.ref	Mfunc_c1, Mfunc_c2, Mfunc_c3, Mfunc_p	;Inputs  
		.ref	limit									;Input


		.ref	BC_INIT,BC_CALC		                    ;function call
		.ref	BC_IN,BC_OUT		                    ;Inputs/Outputs


		.ref	DATA_LOG, DATA_LOG_INIT				;function call
		.ref	dlog_iptr1, dlog_iptr2				;Inputs
		.ref	trig_value							;Inputs

;-----------------------------------------------------------------------------
; Local Variable Declarations
;-----------------------------------------------------------------------------
		.def	GPR0			;General purpose registers.
		.def	GPR1
		.def	GPR2
		.def	GPR3
		.def	GPR4
        .def    rpm_scaler
        .def	speed_rpm_old     
        
        .def	COMCON

		.bss	GPR0,1		;General purpose registers.
		.bss	GPR1,1
		.bss	GPR2,1
		.bss	GPR3,1
		.bss	GPR4,1

		.bss	closed_loop_flag,1
		.bss	freq_in,1
		.bss	speed_setpt,1
        .bss    rpm_scaler,1
       	.bss	speed_rpm_old,1    
       	.bss	direction,1
 		.bss	Van,1
		.bss	Vbn,1
		.bss	Vcn,1
		.bss	Vab,1
		.bss	Vbc,1
		.bss	Vca,1	
		.bss	HALF,1
		.bss	MINUS_ONE,1	      	
		.bss	isr_ticker,1
		
;==============================================================================
; V E C T O R    T A B L E    ( including RT monitor traps )
;==============================================================================
          	.include "c200mnrt.i" 	; Include conditional assembly options.

		.sect "vectors"  
		.def 	_c_int0

RESET	    B	  _c_int0 	 		; 00
INT1	    B	  PHANTOM	 		; 02
INT2	    B	  T1UF_ISR		        ; 04
INT3	    B	  PHANTOM	 		; 06
INT4	    B	  PHANTOM			; 08
INT5	    B	  PHANTOM	 		; 0A
INT6	    B	  PHANTOM	 		; 0C

		.include	"rtvecs.h"

; Note : The above include line must be AFTER the user configurable 
;        vectors. Do not change the place where this line is included.

;==============================================================================
; M A I N   C O D E  - starts here
;==============================================================================
		.text
_c_int0:
		CALL	SYS_INIT
		CALL	RAMP_CNTL_INIT
		CALL	V_Hz_PROFILE_INIT
		CALL	SVGEN_MF_INIT
		CALL	SPEED_PRD_INIT
		CALL	CAP_EVENT_DRV_INIT
		CALL	FC_PWM_O_DRV_INIT
        CALL    BC_INIT
        CALL	D_PID_REG_INIT
		CALL	DATA_LOG_INIT

;------------------------------------------------------
;System time-base init - Timer2
;------------------------------------------------------
SYSTEM_INT_PERIOD	.set	1000		;set for 50uS period @50nS CPU clock

;---Real Time option---------------
	.if (real_time)
		CALL	MON_RT_CNFG		;For Real-Time
	.endif
;----------------------------------
            
; Initializing speed set point

		POINT_B0
		lacc	#1200
		sacl	speed_setpt
;----------------------------------------------------------
; System Interrupt Init.
;----------------------------------------------------------
	;Event Manager
		POINT_EV
		SPLK	#0000001000000000b,IMRA ;Enable T1 Underflow Int (i.e. Period)
;		SPLK	#0000001000000001b,IMRA ;Enable T1 Underflow Int (i.e. Period)
;		SPLK	#0000000000000100b,IMRB ;Enable T2 Underflow Int (i.e. Period)
;		SPLK	#0000000000000100b,IMRC ;Enable CAP3 int (i.e. QEP index pulse)
			    ;||||!!!!||||!!!!		
			    ;5432109876543210

		SPLK	#0FFFFh,IFRA	; Clear all Group A interrupt flags
		SPLK	#0FFFFh,IFRB	; Clear all Group B interrupt flags
		SPLK	#0FFFFh,IFRC	; Clear all Group C interrupt flags

	;C2xx Core
		POINT_PG0

;---Real Time option --------------------------------------------------
	.if (real_time)
		SPLK	#0000000001000010b,IMR	;En Int lvl 2,7 (T1 ISR)
			     ;5432109876543210
	.endif


	.if (real_time != 1)
		SPLK	#0000000000000010b,IMR	;En Int lvl 2 (T1 ISR)
;		SPLK	#0000000000000100b,IMR	;En Int lvl 3 (T2 ISR)
			;||||!!!!||||!!!!		
			;5432109876543210
	.endif

		SPLK	#0FFFFh, IFR		;Clear any pending Ints
		EINT					;Enable global Ints
		POINT_B0
;-----------------------------------------------------------------------

;-----------------------------------------------------------------------
;Enables PWM signals on DMC1500  
;-----------------------------------------------------------------------
	.if (x243|x2407)		;target dependancy
		POINT_PF2
		LACC	OCRA
		AND		#0BFFFh	
		SACL	OCRA			;Select Secondary function IOPB6

		LACC	PBDATDIR
		OR		#04000h
		SACL	PBDATDIR		;Set IOPB6 as output

		LACC	PBDATDIR
		AND		#0FFBFh     	;Set IOPB6 low, Enable PWM
;       OR		#00040h     	;Set IOPB6 high, Disable PWM
		SACL	PBDATDIR  	
	.endif

;---------------------------------------------------------
;SYSTEM COMMISSIONING OPTIONS - Initialisation
;---------------------------------------------------------
		POINT_B0   
	
	.if (phase1_commissioning)     
RPM_SCALER		.set	5501h

		SPLK	#7FFFh, Mfunc_p
		SPLK	#1000h, freq_in   
		SPLK	#RPM_SCALER, rpm_scaler
		SPLK	#0500h, GPR0

	.endif
;---------------------------------------------------------
;---------------------------------------------------------
	.if (phase2_commissioning)

RPM_SCALER		.set	5510h

		SPLK	#7FFFh, Mfunc_p
		SPLK	#1000h, freq_in   
		SPLK	#RPM_SCALER, rpm_scaler
		SPLK	#0, direction
		            
	.endif
;---------------------------------------------------------
	.if (phase3_commissioning)

RPM_SCALER	.set	5510h			;13.1 (Q11) x 3048/32767 (Q15) = 7FFFh (Q15)

		SPLK	#7FFFh, Mfunc_p
		SPLK	#1000h, freq_in
        SPLK    #RPM_SCALER,rpm_scaler
        SPLK	#0, closed_loop_flag	;start in open loop mode
                

	.endif
;---------------------------------------------------------

;======================================================
MAIN:		;Main system background loop
;======================================================

M_1		B	MAIN
;======================================================


;===========================================================================
; Routine Name: T1UF_ISR				     Routine Type: ISR
;
; Description:
;
;
; Originator: Digital control systems Group - Texas Instruments
;
; History:
;
;
; Last Update:	08-25-2000
;===========================================================================
T1UF_ISR:
;Context save regs
		MAR	*,AR1			;AR1 is stack pointer
		MAR	*+          	;skip one position
		SST	#1, *+      	;save ST1
		SST   #0, *+      	;save ST0
		SACH	*+          ;save acc high
		SACL	*			;save acc low

		POINT_EV
		SPLK	#0FFFFh,IFRA  	; Clear all Group A interrupt flags (T1 ISR)

;=========================================================
;Start main section of ISR
;=========================================================
		POINT_B0
		
		; verifying the ISR
		LACC 	isr_ticker	
		ADD		#1			
		SACL    isr_ticker   
		       
;---------------------------------------------------------
;SYSTEM COMMISSIONING OPTIONS - Main code
;---------------------------------------------------------
	;Check interrupts, DAC o/ps, general TI/PI blocks.
	;This phase will operate on any 24x/xx device.

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