srl2pal.ncf

来自「设计与验证verilog hdl」· NCF 代码 · 共 22 行

#
# Constraints generated by Synplify Pro 8.1.0, Build 540R
#

# Period Constraints

#Begin clock constraints
NET "clk" TNM_NET = "clk"; 
TIMESPEC "TS_clk" = PERIOD "clk" 1.446 ns HIGH 50.00%; 
#End clock constraints

# Output Constraints
# Input Constraints

# I/O Registers Packing Constraints
INST "pal_out[7]" IOB=FALSE;
INST "pal_out[0]" IOB=FALSE;

# Location Constraints

# End of generated constraints