mod_copy2.srr

设计与验证verilog hdl

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Wed Mar 08 17:58:58 2006

Synplicity Verilog Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@I::"C:\eda\synplicity\fpga_81\lib\lucent\xp.v"
@I::"C:\prj\Chapter5\Example-5-7\source\mod_copy2.v"
Verilog syntax check successful!
File C:\prj\Chapter5\Example-5-7\source\mod_copy2.v changed - recompiling
Selecting top level module mod_copy1
@N:"C:\prj\Chapter5\Example-5-7\source\mod_copy2.v":1:7:1:15|Synthesizing module mod_copy1

@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Mar 08 17:58:58 2006

###########################################################[
Version 8.1
Synplicity Lattice ORCA FPGA Technology Mapper, Version 8.1.0, Build 532R, Built Apr 28 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
Setting fanout limit to 100
Starting Generic Flow
@N: MT204 |Autoconstrain Mode is ON
@N|Only System clock will be Autoconstrained
---------------------------------------
Resource Usage Report
Part: lfxp10c-3

Register bits: 0 of 9728 (0%)
I/O cells:       6

Details:
IB:             5
OB:             1
ORCALUT4:       2
VHI:            1
VLO:            1


##### START OF TIMING REPORT #####[
# Timing Report written on Wed Mar 08 17:59:00 2006
#


Top view:               mod_copy1
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: NA






Interface Information 
*********************

		No IO constraint found 


##### END OF TIMING REPORT #####]

Mapper successful!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
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