📄 cpu.vhd
字号:
CJNE_IR1_N | CJNE_R0_N |
CJNE_R1_N | CJNE_R2_N |
CJNE_R3_N | CJNE_R4_N |
CJNE_R5_N | CJNE_R6_N |
CJNE_R7_N | DJNZ_ADDR |
LCALL
=>
if curcycle=1 or curcycle=2 then
pc_inc_e <= '1';
else
pc_inc_e <= '0';
end if;
when others => -- instrreg
if curcycle=1 or curcycle=3 then
pc_inc_e <= '1';
else
pc_inc_e <= '0';
end if;
end case;
when others => -- nr bytes
pc_inc_e <= '0';
end case;
else
pc_inc_e <= '0';
end if; -- phase=4
end process;
--------------------------------------------------------------------
-- Program Counter increment enable - registered section
--------------------------------------------------------------------
pcince_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
pcince <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
if ( ( (debugprog='0' and debugprogff='0'
) and
(debugreq='1' or debugmode='1'
) and
(debugstepff='1' or debugstep='1'
)
) or -- debugger mode, user program
(debugmode='0' and not(curcycle=nr_cycles)
) or
(debugreq='0' and debugmode='0'
)
) and
( ( (curcycle=nr_cycles and
curphase=4) and -- codefetche
intreq='0'
) or
pc_inc_e = '1' -- datafetche
) and int_call='0'
then
pcince <= '1';
else
pcince <= '0';
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- Instruction Register
--------------------------------------------------------------------
instrreg_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
instrreg <= NOP;
else
-------------------------------------
-- Synchronous write
-------------------------------------
-- Instruction register write
----------------------------------
if codefetche_ff='1' then
if debugmode='1' and debugstep='0' and debugstepff='0' then
instrreg <= NOP;
elsif intreq='1' then -- Interrupt request
instrreg <= LCALL;
else
if memdatai=UNKNOWN then
instrreg <= NOP;
else
instrreg <= memdatai;
end if;
end if;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- Current machine cycle counter
--------------------------------------------------------------------
curcycle_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' and par_cycle='0' then
curcycle <= 1;
else
-------------------------------------
-- Synchronous write
-------------------------------------
-- Current cycle count
----------------------------------
if (curphase=6) then
if (curcycle<nr_cycles) then
curcycle <= curcycle + 1;
else
curcycle <= 1;
end if;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- Current phase of cycle
--------------------------------------------------------------------
curphase_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
-------------------------------------
-- Synchronous write
-------------------------------------
-- Current phase count
----------------------------------
case curphase is
when 1 =>
curphase <= 2;
when 2 =>
curphase <= 3;
when 3 =>
curphase <= 4;
when 4 =>
curphase <= 5;
when 5 =>
curphase <= 6;
when others =>
curphase <= 1;
end case;
end if;
end process;
--------------------------------------------------------------------
-- Parity cycle indicator
--------------------------------------------------------------------
par_cycle_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
-------------------------------------
-- Synchronous write
-------------------------------------
if curphase = 6 then
if par_cycle= '0' then
par_cycle <= '1';
else
par_cycle <= '0';
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- Read-Modify-Write instructions
--------------------------------------------------------------------
rmwinstr_decoder_hand:
--------------------------------------------------------------------
rmwinstr_a <=
'1' when (memdatai=ANL_ADDR_A or
memdatai=ANL_ADDR_N or
memdatai=ORL_ADDR_A or
memdatai=ORL_ADDR_N or
memdatai=XRL_ADDR_A or
memdatai=XRL_ADDR_N or
memdatai=JBC_BIT or
memdatai=CPL_BIT or
memdatai=INC_ADDR or
memdatai=DEC_ADDR or
memdatai=DJNZ_ADDR or
memdatai=MOV_BIT_C or
memdatai=CLR_BIT or
memdatai=SETB_BIT
) else
'0';
--------------------------------------------------------------------
-- Read-Modify-Write instructions flip-flop
--------------------------------------------------------------------
rmwinstr_decoder_proc:
--------------------------------------------------------------------
process (clk)
begin
if (clk'event and clk='1') then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
rmwinstr <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
-- Read-Modify-Write flip-flop
----------------------------------
if codefetche_ff='1' then --or debugfetche_ff='1' then
rmwinstr <= rmwinstr_a;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
nr_decoder_hand:
--------------------------------------------------------------------
process (memdatai)
begin
case memdatai is
-------------------------------------
-- 00h
-------------------------------------
when NOP =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when AJMP_0 =>
nr_bytes_a <= 2;
nr_cycles_a <= 4;
when LJMP =>
nr_bytes_a <= 3;
nr_cycles_a <= 4;
when RR_A =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when INC_A =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when INC_ADDR =>
nr_bytes_a <= 2;
nr_cycles_a <= 2;
when INC_IR0 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when INC_IR1 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when INC_R0 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when INC_R1 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when INC_R2 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when INC_R3 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when INC_R4 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when INC_R5 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when INC_R6 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when INC_R7 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
-------------------------------------
-- 10h
-------------------------------------
when JBC_BIT =>
nr_bytes_a <= 3;
nr_cycles_a <= 4;
when ACALL_0 =>
nr_bytes_a <= 2;
nr_cycles_a <= 4;
when LCALL =>
nr_bytes_a <= 3;
nr_cycles_a <= 4;
when RRC_A =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when DEC_A =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when DEC_ADDR =>
nr_bytes_a <= 2;
nr_cycles_a <= 2;
when DEC_IR0 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when DEC_IR1 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when DEC_R0 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when DEC_R1 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when DEC_R2 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when DEC_R3 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when DEC_R4 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when DEC_R5 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when DEC_R6 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when DEC_R7 =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
-------------------------------------
-- 20h
-------------------------------------
when JB_BIT =>
nr_bytes_a <= 3;
nr_cycles_a <= 4;
when AJMP_1 =>
nr_bytes_a <= 2;
nr_cycles_a <= 4;
when RET =>
nr_bytes_a <= 1;
nr_cycles_a <= 4;
when RL_A =>
nr_bytes_a <= 1;
nr_cycles_a <= 2;
when ADD_N =>
nr_bytes_a <= 2;
nr_cycles_a <= 2;
when ADD_ADDR =>
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