📄 cpu.vhd
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--*******************************************************************--
-- Copyright (c) 1999-2001 Evatronix SA --
--*******************************************************************--
-- Please review the terms of the license agreement before using --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you --
-- inadvertently received an unauthorized copy. --
--*******************************************************************--
-----------------------------------------------------------------------
-- Project name : C8051
-- Project description : C8051 Microcontroller Unit
--
-- File name : CPU.VHD
-- File contents : Entity CONTROL_UNIT
-- Architecture RTL of CONTROL_UNIT
-- Purpose : Control Processor Unit
--
-- Destination library : C8051_LIB
-- Dependencies : C8051_LIB.Utility
-- IEEE.STD_LOGIC_1164
--
-- Design Engineer : M.B. D.K.
-- Quality Engineer : M.B.
-- Version : 3.01.E00
-- Last modification : 2001-10-01
-----------------------------------------------------------------------
--*******************************************************************--
-- Modifications with respect to Version 3.00.E00:
-- 3.01.E00 :
-- 2001-10-01 : added OCI ports: debugreq, debugprog, debugprogff,
-- : debugstep, debugstepff, debugmode
-- 2001-10-01 : added output ports: nrcycles, codefetcheff
-- 2001-10-01 : write of int_call signal modified in respect to OCI
-- 2001-10-01 : pcince_write_proc, instrreg_proc, rmwinstr_decoder_proc
-- : nr_decoder_proc modified in respect to OCI
--*******************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library C8051_LIB;
use C8051_LIB.UTILITY.all;
--*******************************************************************--
entity CONTROL_UNIT is
port (
-- Control signal inputs
clk : in STD_LOGIC; -- Global clock input
rst : in STD_LOGIC; -- Global reset input
-- ISR input signals
intreq : in STD_LOGIC; -- Interrupt request
-- OCI ports
debugreq : in STD_LOGIC;
debugprog : in STD_LOGIC;
debugprogff : in STD_LOGIC;
debugstep : in STD_LOGIC;
debugstepff : in STD_LOGIC;
debugmode : in STD_LOGIC;
-- Instruction register output
instr : out STD_LOGIC_VECTOR(7 downto 0);
-- Cycle counter output
cycle : out INTEGER range 1 to 8;
nrcycles : out INTEGER range 1 to 8;
phase : out INTEGER range 1 to 6;
parcycle : out STD_LOGIC; -- parity cycle indicator
-- program counter increment enable
pcince : out STD_LOGIC;
-- Instruction decoder output
codefetche : out STD_LOGIC; -- Opcode fetch enable
codefetcheff : out STD_LOGIC; -- Opcode fetch enable flip-flop
datafetche : out STD_LOGIC; -- Data fetch enable
rmwinstr : out STD_LOGIC; -- Read-Modify-Write Instr.
-- ISR control outputs
intack : out STD_LOGIC; -- Interrupt acknowledge flag
intret : out STD_LOGIC; -- Interrupt return flag
intcall : out STD_LOGIC; -- Interrupt call routine
-- Program bus input
memdatai : in STD_LOGIC_VECTOR(7 downto 0)
);
end CONTROL_UNIT;
--*******************************************************************--
architecture RTL of CONTROL_UNIT is
-----------------------------------------------------------------
-- Instruction register
-----------------------------------------------------------------
signal instrreg : STD_LOGIC_VECTOR(7 downto 0);
-----------------------------------------------------------------
-- Fetch enable signals
-----------------------------------------------------------------
signal code_fetch_e : STD_LOGIC; -- combinational
signal data_fetch_e : STD_LOGIC; -- combinational
signal codefetche_ff : STD_LOGIC; -- registered
-----------------------------------------------------------------
-- Current machine cycle register
-----------------------------------------------------------------
signal curcycle : INTEGER range 1 to 8;
signal curphase : INTEGER range 1 to 6;
-----------------------------------------------------------------
-- Parity cycle indicator
-----------------------------------------------------------------
signal par_cycle : STD_LOGIC;
-----------------------------------------------------------------
-- Number of bytes and cycles
-----------------------------------------------------------------
signal nr_cycles_a : INTEGER range 1 to 8; -- combinational
signal nr_bytes_a : INTEGER range 1 to 6; -- combinational
signal nr_cycles : INTEGER range 1 to 8; -- registered
signal nr_bytes : INTEGER range 1 to 6; -- registered
-----------------------------------------------------------------
-- Read-Modify-Write Instruction signal
-----------------------------------------------------------------
signal rmwinstr_a : STD_LOGIC; -- combinational
-----------------------------------------------------------------
-- Interrupt call routine
-----------------------------------------------------------------
signal int_call : STD_LOGIC;
-----------------------------------------------------------------
-- increment pc register
-----------------------------------------------------------------
signal pc_inc_e : STD_LOGIC;
begin
--------------------------------------------------------------------
-- Code fetch enable flip-flop
--------------------------------------------------------------------
codefetcheff_drv:
--------------------------------------------------------------------
codefetcheff <= codefetche_ff;
--------------------------------------------------------------------
-- Instruction register
--------------------------------------------------------------------
instr_drv:
--------------------------------------------------------------------
instr <= instrreg;
--------------------------------------------------------------------
-- Current machine cycle register
--------------------------------------------------------------------
cycle_drv:
--------------------------------------------------------------------
cycle <= curcycle;
--------------------------------------------------------------------
-- Number of current instruction cycles register
--------------------------------------------------------------------
nrcycles_drv:
--------------------------------------------------------------------
nrcycles <= nr_cycles;
--------------------------------------------------------------------
-- Current phase of cycle register
--------------------------------------------------------------------
phase_drv:
--------------------------------------------------------------------
phase <= curphase;
--------------------------------------------------------------------
-- Parity cycle indicator register
--------------------------------------------------------------------
parcycle_drv:
--------------------------------------------------------------------
parcycle <= par_cycle;
--------------------------------------------------------------------
-- Opcode fetch enable
--------------------------------------------------------------------
codefetche_drv:
--------------------------------------------------------------------
codefetche <= code_fetch_e;
--------------------------------------------------------------------
-- Data fetch enable
--------------------------------------------------------------------
datafetche_drv:
--------------------------------------------------------------------
datafetche <= data_fetch_e;
--------------------------------------------------------------------
-- Interrupt call routine register
--------------------------------------------------------------------
intcall_drv:
--------------------------------------------------------------------
intcall <= int_call;
--------------------------------------------------------------------
-- interrupt handling registers
--------------------------------------------------------------------
interrupt_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
intack <= '0';
intret <= '0';
int_call <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
-- Interrupt acknowledge flag
----------------------------------
if (int_call='1' and
curcycle=3 and
curphase=4)
then
intack <= '1'; -- Interrupt acknowledge
else
intack <= '0';
end if;
----------------------------------
-- Interrupt return flag
----------------------------------
if (instrreg=RETI and
curcycle=4 and
curphase=5
) then
intret <= '1'; -- Interrupt return
else
intret <= '0';
end if;
----------------------------------
-- Interrupt call routine
----------------------------------
if codefetche_ff='1' and intreq='1' and debugmode='0' -- Interrupt request
then
int_call <= '1';
elsif int_call='1' and
curcycle=4 and
curphase=3
then
int_call <= '0'; -- Interrupt call subroutine
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- Opcode fetch enable
--------------------------------------------------------------------
code_fetch_e_hand:
--------------------------------------------------------------------
code_fetch_e <=
'1' when (curcycle=nr_cycles and
curphase=5
) else
'0';
--------------------------------------------------------------------
codefetche_ff_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
codefetche_ff <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
codefetche_ff <= code_fetch_e;
end if;
end if;
end process;
--------------------------------------------------------------------
-- Data fetch enable
--------------------------------------------------------------------
data_fetch_e_hand:
--------------------------------------------------------------------
data_fetch_e <=
'1' when (curcycle<nr_bytes and
curphase=5
) else
'0';
--------------------------------------------------------------------
-- Program Counter increment enable - combinationar section
--------------------------------------------------------------------
pc_inc_e_proc:
--------------------------------------------------------------------
process(nr_bytes, nr_cycles, instrreg, curcycle, curphase)
begin
if curphase=4 then
case nr_bytes is
when 2 =>
case nr_cycles is
when 2 =>
if curcycle=1 then
pc_inc_e <= '1';
else
pc_inc_e <= '0';
end if;
when 4 =>
case instrreg is
when
AJMP_0 | AJMP_1 |
AJMP_2 | AJMP_3 |
AJMP_4 | AJMP_5 |
AJMP_6 | AJMP_7 |
ACALL_0 | ACALL_1 |
ACALL_2 | ACALL_3 |
ACALL_4 | ACALL_5 |
ACALL_6 | ACALL_7 =>
if curcycle=1 then
pc_inc_e <= '1';
else
pc_inc_e <= '0';
end if;
when
MOV_BIT_C | ORL_C_BIT |
ORL_C_NBIT | ANL_C_BIT |
ANL_C_NBIT | PUSH |
POP | MOV_ADDR_R0 |
MOV_ADDR_R1 | MOV_ADDR_R2 |
MOV_ADDR_R3 | MOV_ADDR_R4 |
MOV_ADDR_R5 | MOV_ADDR_R6 |
MOV_ADDR_R7
=>
if curcycle=3 then
pc_inc_e <= '1';
else
pc_inc_e <= '0';
end if;
when others => --instrreg
if curcycle=2 then
pc_inc_e <= '1';
else
pc_inc_e <= '0';
end if;
end case;
when others => -- nr_cycles
pc_inc_e <= '0';
end case;
when 3 => -- nr_bytes
case instrreg is
when
JB_BIT | JBC_BIT |
JNB_BIT | CJNE_A_N |
CJNE_A_ADDR | CJNE_IR0_N |
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