memctrl.vhd

51单片机内核vhdl实现 xilinx平台的

      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               memrd <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if (instr=MOVX_A_IR0 or
                   instr=MOVX_A_IR1 or
                   instr=MOVX_A_IDPTR
                  ) and
                  ( 
                     (
                        (cycle=2) and
                        (phase=5 or
                         phase=6)
                     ) or
                     (
                        (cycle=3) and
                        (phase=1 or
                         phase=2 or
                         phase=3 or
                         phase=4 
                        )
                     )
                  ) 
               then
                  memrd <= '1';
               else
                  memrd <= '0';
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- External memory accsess via Port 0
   --  registered output
   --  high active
   --------------------------------------------------------------------
   memp0acs_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               memp0acs <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if (------------------------  
                   -- MOVX Write Cycle   
                   ------------------------
                     (instr=MOVX_IR0_A or
                      instr=MOVX_IR1_A or
                      instr=MOVX_IDPTR_A
                     ) and
                     ( ( (cycle=3) and
                             ((phase=5) or
                                 (phase=4) or
                                 (phase=3) or
                                 (phase=2) or
                                 (phase=1)
                             ) 
                          ) or
                       cycle=2
                     )
                  -------------------------
                  -- MOVX Read Cycle     
                  -------------------------
                  ) or
                  (
                     (instr=MOVX_A_IR0 or
                      instr=MOVX_A_IR1 or
                      instr=MOVX_A_IDPTR
                     ) and
                     ( (cycle=2) and
                          ( (phase=1) or
                               (phase=2)
                          )
                     ) 
                  -------------------------
                  -- External ROM fetches
                  -------------------------
                  ) or
                  ( ( ( (intromsel='0') and
                             ( (phase=2) or
                                  (  (phase=1) and not
                                        ( (memaddrbuff&mem_addr(7 downto 0)<
                                             INTROMAREA) and
                                             (ea='1') and
                                             (addr_chk='1')
                                        )
                                  )
                             ) 
                          )
                       ) and not
                       ( (instr=MOVX_A_IR0 or
                            instr=MOVX_A_IR1 or
                            instr=MOVX_A_IDPTR
                            ) and
                            (cycle=3)
                       ) 
                  -------------------------
                  -- Internal ROM fetches
                  -------------------------
                  ) or
                  ( (intromsel='1') and
                       ( not(memaddrbuff&mem_addr(7 downto 0)<
                             INTROMAREA)
                       )and
                       (addr_chk='1')
                  )
               then
                  memp0acs <= '1';
               else
                  memp0acs <= '0';
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- External memory accsess via Port 2
   --  registered output
   --  high active
   --------------------------------------------------------------------
   memp2acso_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               memp2acso <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if -------------------------
                  -- MOVX Cycles
                  -------------------------
                  ( (instr=MOVX_A_IR0 or
                       instr=MOVX_A_IR1 or
                       instr=MOVX_A_IDPTR or
                       instr=MOVX_IR0_A or
                       instr=MOVX_IR1_A or
                       instr=MOVX_IDPTR_A
                       ) and
                       ( ( (cycle=2) 
                            ) or
                            (cycle=3
                            )
                       )
                  -------------------------
                  -- External ROM Fetches
                  -------------------------
                  ) or
                  ( (intromsel='0') and not
                       ( (memaddrbuff&mem_addr(7 downto 0)<
                            INTROMAREA) and
                            (ea='1') and
                            (addr_chk='1')
                       )
                  -------------------------
                  -- Internal ROM Fetches
                  -------------------------
                  ) or
                  ( (intromsel='1') and
                       (not (memaddrbuff&mem_addr(7 downto 0)<
                             INTROMAREA)
                       )and
                       (addr_chk='1')
                  )
               then
                  memp2acso <= '1';
               else
                  memp2acso <= '0';
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Address/Data bus select
   --  registered output
   --  high active
   --------------------------------------------------------------------
   addrdatasel_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               addrdatasel <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if (  (  (phase=4 or 
                           phase=5 or 
                           phase=6
                           ) and 
                        cycle=2
                        ) or
                        (cycle=3)
                  ) and
                  (instr=MOVX_IR0_A or
                   instr=MOVX_IR1_A or
                   instr=MOVX_IDPTR_A
                  )
               then
                  addrdatasel <= '0';
               else
                  addrdatasel <= '1';
               end if;
            end if;
         end if;
      end process;
      
   --------------------------------------------------------------------
   -- flush flip-flop
   --------------------------------------------------------------------
   flushff_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               flushff <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if pcrele='1' or dpadde='1' or buffsel='1' then
                  flushff <= '1';
               elsif codefetche='1' then
                  if (debugmode='1' and debugstepff='1') or
                     debugmode='0'
                  then
                     flushff <= '0';
                  end if;
               end if;
            end if;
         end if;
      end process;
   
   --------------------------------------------------------------------
   -- External Program Store Enable
   --  registered output
   --  low active
   --------------------------------------------------------------------
   psen_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               psen <= '1';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if (intromsel='0') and
                  (phase=3 or
                   phase=4 or
                   phase=5
                  ) and
               not (  (instr=MOVX_IR0_A or
                         instr=MOVX_IR1_A or
                         instr=MOVX_IDPTR_A
                         ) and
                         (cycle=2 or
                          cycle=3)
                   ) and
               not (  (instr=MOVX_A_IR0 or
                         instr=MOVX_A_IR1 or
                         instr=MOVX_A_IDPTR
                         ) and
                         (cycle=2 or
                          cycle=3)
                   )
               then
                  psen <= '0';
               else
                  psen <= '1';
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- External Address Latch Enable
   --  registered output on rising edge of clk
   --  high active
   --------------------------------------------------------------------
   ale_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               ale <= '1';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if (phase=6 or 
                   phase=1
                  ) and
               not (
                      (instr=MOVX_IR0_A or
                       instr=MOVX_IR1_A or
                       instr=MOVX_IDPTR_A
                      ) and
                      ( (cycle=2 and phase=6) or
                           (cycle=3 and phase=1)
                      )
                   ) and
               not (
                      (instr=MOVX_A_IR0 or
                       instr=MOVX_A_IR1 or
                       instr=MOVX_A_IDPTR
                      ) and
                      ( (cycle=2 and phase=6) or
                           (cycle=3 and phase=1)
                      )
                   )
               then
                  ale <= '1';
               else
                  ale <= '0';
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Special Function registers read
   --------------------------------------------------------------------
   sfr_read :
   --------------------------------------------------------------------
      sfrdatamcu <=
         dptr( 7 downto 0) when sfraddr=DPL_ID   else
         dptr(15 downto 8) when sfraddr=DPH_ID   else
         "--------";
   
   end RTL;
--*******************************************************************--