memctrl.vhd

51单片机内核vhdl实现 xilinx平台的

            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Data Pointer incremented buffer
   --------------------------------------------------------------------
   dp_inc_proc:
   --------------------------------------------------------------------
      process (dptr)
      begin
         dp_inc <= dptr + '1';
      end process;
   
   
   --------------------------------------------------------------------
   -- Data Pointer added buffer
   --------------------------------------------------------------------
   dp_add_hand :
   --------------------------------------------------------------------
      process (dptr, accreg)
      begin
         dp_add <= dptr + accreg;
      end process;
   
   
   --------------------------------------------------------------------
   dp_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               dptr( 7 downto 0) <= DPL_RV;
               dptr(15 downto 8) <= DPH_RV;
            else
            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- Data Pointer increment or load
               ----------------------------------
               if dpince='1' then   -- DPTR=DPTR+1
                  dptr <= dp_inc;
               elsif dplwe='1' then -- MOV_DPTR_N
                  dptr(7 downto 0) <= memdatai;
               elsif dphwe='1' then
                  dptr(15 downto 8) <= memdatai;
               else
               
               ----------------------------------
               -- Special function register write
               ----------------------------------
                  if (sfrwe='1' and sfraddr=DPL_ID) then
                     dptr(7 downto 0) <= sfrdatai;
                  end if;
                  if (sfrwe='1' and sfraddr=DPH_ID) then
                     dptr(15 downto 8) <= sfrdatai;
                  end if;
               end if;
            
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Program Memory Address Write
   --------------------------------------------------------------------
   addr_sel_hand:
   --------------------------------------------------------------------
      addr_sel <= pcaddsel&dpsel&dpaddsel&risel&pcsel&buffsel;   
   --------------------------------------------------------------------
   mem_addr_write1_proc:
   --------------------------------------------------------------------
      process (clk)      
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               mem_addr(7 downto 0) <= "00000000";
               memaddrbuff(7 downto 0) <= "00000000";
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- Special function register write
               ----------------------------------
               case addr_sel is                      --ADDR=PC+A
                  when "100000" | "100010" =>        -- pcaddsel='1' 
                     mem_addr(7 downto 0) <= pc_add(7 downto 0);
                     memaddrbuff(7 downto 0) <= pc_add(15 downto 8);
                                                     -- ADDR=DPTR
                  when "010000" | "010010" =>        -- dpsel='1'    
                     mem_addr(7 downto 0) <= dptr(7 downto 0);
                     memaddrbuff(7 downto 0) <= dptr(15 downto 8);
                                                     -- ADDR=DPTR+A
                  when "001000" | "001010" =>        -- dpaddsel='1' 
                     mem_addr(7 downto 0) <= dp_add(7 downto 0);
                     memaddrbuff(7 downto 0) <= dp_add(15 downto 8);
                                                     -- ADDR(low)=Ri
                  when "000100" | "000110" =>        -- risel='1'    
                     mem_addr(7 downto 0) <= sfrdatai; 
                     memaddrbuff(7 downto 0) <= p2reg;
                                                     -- ADDR=PC
                  when "000010" =>                   -- pcsel='1'    
                     mem_addr(7 downto 0) <= pc(7 downto 0);
                     memaddrbuff(7 downto 0) <= pc(15 downto 8);
                                                     -- ADDR=buff 
                  when "000001" | "000011" =>        -- buffsel='1'  
                     mem_addr(7 downto 0) <= addrbuff(7 downto 0);
                     memaddrbuff(7 downto 0) <= addrbuff(15 downto 8);
               
                  when others =>
                     null;
               
               end case;
            
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- memory address high byte write (one clock period delay)
   --------------------------------------------------------------------
   mem_addr_write2_proc:
   --------------------------------------------------------------------
      process (clk)      
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               mem_addr(15 downto 8) <= "00000000";
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- Special function register write
               ----------------------------------
               mem_addr(15 downto 8) <= memaddrbuff(7 downto 0);
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Relative address register write
   --------------------------------------------------------------------
   rel_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               rel <= "00000000";
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- Relative address register write
               ----------------------------------
               if relwe='1' then
                  rel <= memdatai;
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Address buffer register write
   --------------------------------------------------------------------
   addrbuff_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               addrbuff <= "0000000000000000";
            else
            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- Address buffer register write
               ----------------------------------
               if intcall='1' then  -- Interrupt request
                  addrbuff(7 downto 0) <= "00" & intvect & "011";
               elsif membufflwe='1' then
                  addrbuff(7 downto 0) <= memdatai;
               elsif rambufflwe='1' then
                  addrbuff(7 downto 0) <= ramdatai;
               end if;
               if intcall='1' then  -- Interrupt request
                  addrbuff(15 downto 8) <= "00000000";
               elsif membuffhwe='1' then
                  addrbuff(15 downto 8) <= memdatai;
               elsif rambuffhwe='1' then
                  addrbuff(15 downto 8) <= ramdatai;
               elsif instrbuffwe='1' then
                  addrbuff(10 downto 8)  <= instr(7 downto 5);
                  addrbuff(15 downto 11) <= pc(15 downto 11);
               end if;
            
            end if;
         end if;
      end process;   
   
   
   --------------------------------------------------------------------
   -- memory address check 
   --  high active 
   --------------------------------------------------------------------
   addr_chk_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               addr_chk <= '1';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if (pcaddsel='1') or  -- MOVC_A_PC
                  (buffsel='1')  or 
                  (dpaddsel='1') or  -- JMP_A_DPTR or MOVC_A_DPTR
                  (pcsel='1')
               then 
                  addr_chk <= '1';
               else
                  addr_chk <='0';
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- internal ROM access
   --  high active
   --------------------------------------------------------------------
   intromsel_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               intromsel <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if addr_chk='1' then
                  if (memaddrbuff&mem_addr(7 downto 0)<INTROMAREA) and 
                     (ea='1') 
                  then
                     intromsel <= '1';
                  else
                     intromsel <= '0';
                  end if;
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Inernal ROM output enable
   --  registered output
   --  high active
   --------------------------------------------------------------------
   rom_oe_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               rom_oe <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if ( (codefetche='1' or datafetche='1') or
                       (  (instr=MOVC_A_DPTR or instr=MOVC_A_PC) and  
                             (cycle=3 and phase=5)
                       )
                  )
               and
               intromsel='1' then
                  rom_oe <= '1';
               else
                  rom_oe <= '0';
               end if;
            end if;
         end if;
      end process;   
   
   
   --------------------------------------------------------------------
   -- Memory write enable
   --  registered output
   --  high active
   --------------------------------------------------------------------
   memwr_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               memwr <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if (instr=MOVX_IR0_A or
                   instr=MOVX_IR1_A or
                   instr=MOVX_IDPTR_A
                  ) and
                  ( 
                     (
                        (cycle=2) and
                        (phase=5 or
                         phase=6
                        )
                     ) or
                     (
                        (cycle=3) and
                        (phase=1 or
                         phase=2 or
                         phase=3 or
                         phase=4
                        )
                     )
                  ) 
               then
                  memwr <= '1';
               else
                  memwr <= '0';
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Memory read enable
   --  registered output
   --  high active
   --------------------------------------------------------------------
   memrd_proc:
   --------------------------------------------------------------------