memctrl.vhd

51单片机内核vhdl实现 xilinx平台的

            ------------------------------------- 
               if (instr=MOVC_A_PC and cycle=2 and phase=5)
               then
                  pcaddsel <= '1';
               else
                  pcaddsel <= '0';
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- DPTR + A count enable
   -- MEMADDR=DPTR+A
   --------------------------------------------------------------------
   dpaddsel_hand:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               dpaddsel <= '0';
            else
            -------------------------------------
            -- Synchronous write
            ------------------------------------- 
               if (instr=MOVC_A_DPTR and cycle=2 and phase=5)
               then
                  dpaddsel <= '1';
               else
                  dpaddsel <= '0';
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- DPTR select
   -- MEMADDR=DPTR
   --------------------------------------------------------------------
   dpsel_hand:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               dpsel <= '0';
            else
            -------------------------------------
            -- Synchronous write
            ------------------------------------- 
               if (instr=MOVX_A_IDPTR and cycle=1 and phase=5) or
                  (instr=MOVX_IDPTR_A and cycle=1 and phase=5) 
               then
                  dpsel <= '1';
               else
                  dpsel <= '0';
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Ri select
   -- MEMADDR low = Ri
   --------------------------------------------------------------------
   risel_hand:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               risel <= '0';
            else
            -------------------------------------
            -- Synchronous write
            ------------------------------------- 
               if (instr=MOVX_A_IR0 and cycle=1 and phase=6) or
                  (instr=MOVX_A_IR1 and cycle=1 and phase=6) or
                  (instr=MOVX_IR0_A and cycle=1 and phase=6) or
                  (instr=MOVX_IR1_A and cycle=1 and phase=6) 
               then
                  risel <= '1';
               else
                  risel <= '0';
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- DPTR increment enable
   -- DPTR=DPTR+1
   --------------------------------------------------------------------
   dpince_hand:
   --------------------------------------------------------------------
      dpince <=
         '1' when (instr=INC_DPTR and cycle=1 and phase=1) else
         '0';
   
   
   --------------------------------------------------------------------
   -- DPTR low byte write enable
   --------------------------------------------------------------------
   dplwe_hand:
   --------------------------------------------------------------------
      dplwe <=
         '1' when (instr=MOV_DPTR_N and cycle=2 and phase=6) else
         '0';
   
   
   --------------------------------------------------------------------
   -- DPTR high byte write enable
   --------------------------------------------------------------------
   dphwe_hand:
   --------------------------------------------------------------------
      dphwe <=
         '1' when (instr=MOV_DPTR_N and cycle=1 and phase=6) else
         '0';
   
   
   --------------------------------------------------------------------
   -- Memory to Buffer low write enable
   --------------------------------------------------------------------
   membufflwe_hand:
   --------------------------------------------------------------------
      membufflwe <=
         '1' when (
                     (instr=ACALL_0 and cycle=1 and phase=6) or
                     (instr=ACALL_1 and cycle=1 and phase=6) or 
                     (instr=ACALL_2 and cycle=1 and phase=6) or 
                     (instr=ACALL_3 and cycle=1 and phase=6) or 
                     (instr=ACALL_4 and cycle=1 and phase=6) or 
                     (instr=ACALL_5 and cycle=1 and phase=6) or 
                     (instr=ACALL_6 and cycle=1 and phase=6) or 
                     (instr=ACALL_7 and cycle=1 and phase=6) or 
                     (instr=LCALL   and cycle=2 and phase=6) or 
                     (instr=AJMP_0  and cycle=1 and phase=6) or
                     (instr=AJMP_1  and cycle=1 and phase=6) or 
                     (instr=AJMP_2  and cycle=1 and phase=6) or 
                     (instr=AJMP_3  and cycle=1 and phase=6) or 
                     (instr=AJMP_4  and cycle=1 and phase=6) or 
                     (instr=AJMP_5  and cycle=1 and phase=6) or 
                     (instr=AJMP_6  and cycle=1 and phase=6) or 
                     (instr=AJMP_7  and cycle=1 and phase=6) or 
                     (instr=LJMP    and cycle=2 and phase=6) 
                  ) else
         '0';
   
   
   --------------------------------------------------------------------
   -- Memory to Buffer high write enable
   --------------------------------------------------------------------
   membuffhwe_hand:
   --------------------------------------------------------------------
      membuffhwe <=
         '1' when (
                     (instr=LCALL and cycle=1 and phase=6) or 
                     (instr=LJMP  and cycle=1 and phase=6) 
                  ) else
         '0';
   
   
   --------------------------------------------------------------------
   -- RAM to Buffer low write enable
   --------------------------------------------------------------------
   rambufflwe_hand:
   --------------------------------------------------------------------
      rambufflwe <=
         '1' when (
                     (instr=RET  and cycle=2 and phase=3) or
                     (instr=RETI and cycle=2 and phase=3)
                  ) else
         '0';
   
   
   --------------------------------------------------------------------
   -- RAM to Buffer high write enable
   --------------------------------------------------------------------
   rambuffhwe_hand:
   --------------------------------------------------------------------
      rambuffhwe <=
         '1' when (
                     (instr=RET  and cycle=1 and phase=3) or 
                     (instr=RETI and cycle=1 and phase=3)
                  ) else
         '0';
   
   
   --------------------------------------------------------------------
   -- Instruction opcode to Buffer high write enable
   --------------------------------------------------------------------
   instrbuffwe_hand:
   --------------------------------------------------------------------
      instrbuffwe <=
         '1' when (
                     (instr=ACALL_0 and cycle=2 and phase=4) or
                     (instr=ACALL_1 and cycle=2 and phase=4) or 
                     (instr=ACALL_2 and cycle=2 and phase=4) or 
                     (instr=ACALL_3 and cycle=2 and phase=4) or 
                     (instr=ACALL_4 and cycle=2 and phase=4) or 
                     (instr=ACALL_5 and cycle=2 and phase=4) or 
                     (instr=ACALL_6 and cycle=2 and phase=4) or 
                     (instr=ACALL_7 and cycle=2 and phase=4) or 
                     (instr=AJMP_0  and cycle=2 and phase=4) or
                     (instr=AJMP_1  and cycle=2 and phase=4) or 
                     (instr=AJMP_2  and cycle=2 and phase=4) or 
                     (instr=AJMP_3  and cycle=2 and phase=4) or 
                     (instr=AJMP_4  and cycle=2 and phase=4) or 
                     (instr=AJMP_5  and cycle=2 and phase=4) or 
                     (instr=AJMP_6  and cycle=2 and phase=4) or 
                     (instr=AJMP_7  and cycle=2 and phase=4)
                  ) else
         '0';
   
   
   --------------------------------------------------------------------
   -- Rel register write enable
   --------------------------------------------------------------------
   relwe_hand:
   --------------------------------------------------------------------
      relwe <=
         '1' when (
                     (instr=SJMP        and cycle=1 and phase=6) or
                     (instr=JZ          and cycle=1 and phase=6) or
                     (instr=JNZ         and cycle=1 and phase=6) or
                     (instr=JC          and cycle=1 and phase=6) or
                     (instr=JNC         and cycle=1 and phase=6) or
                     (instr=JB_BIT      and cycle=2 and phase=6) or
                     (instr=JNB_BIT     and cycle=2 and phase=6) or
                     (instr=JBC_BIT     and cycle=2 and phase=6) or
                     (instr=CJNE_A_ADDR and cycle=2 and phase=6) or
                     (instr=CJNE_A_N    and cycle=2 and phase=6) or
                     (instr=CJNE_R0_N   and cycle=2 and phase=6) or
                     (instr=CJNE_R1_N   and cycle=2 and phase=6) or
                     (instr=CJNE_R2_N   and cycle=2 and phase=6) or
                     (instr=CJNE_R3_N   and cycle=2 and phase=6) or
                     (instr=CJNE_R4_N   and cycle=2 and phase=6) or
                     (instr=CJNE_R5_N   and cycle=2 and phase=6) or
                     (instr=CJNE_R6_N   and cycle=2 and phase=6) or
                     (instr=CJNE_R7_N   and cycle=2 and phase=6) or
                     (instr=CJNE_IR0_N  and cycle=2 and phase=6) or
                     (instr=CJNE_IR1_N  and cycle=2 and phase=6) or
                     (instr=DJNZ_R0     and cycle=1 and phase=6) or
                     (instr=DJNZ_R1     and cycle=1 and phase=6) or
                     (instr=DJNZ_R2     and cycle=1 and phase=6) or
                     (instr=DJNZ_R3     and cycle=1 and phase=6) or
                     (instr=DJNZ_R4     and cycle=1 and phase=6) or
                     (instr=DJNZ_R5     and cycle=1 and phase=6) or
                     (instr=DJNZ_R6     and cycle=1 and phase=6) or
                     (instr=DJNZ_R7     and cycle=1 and phase=6) or
                     (instr=DJNZ_ADDR   and cycle=2 and phase=6)
                  ) else
         '0';
   
   
   
   --------------------------------------------------------------------
   -- PC select - combinational section
   -- MEM <- PC
   --------------------------------------------------------------------
   pcsel_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               pcsel <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if (pcince='1') or
                  (pcrele='1') or
                  (
                     (cycle=3) and
                     (phase=5) and
                     (instr=MOVC_A_PC or
                      instr=MOVC_A_DPTR or
                      instr=MOVX_A_IR0 or
                      instr=MOVX_A_IR1 or
                      instr=MOVX_A_IDPTR or
                      instr=MOVX_IDPTR_A or
                      instr=MOVX_IR0_A or
                      instr=MOVX_IR1_A or
                      instr=JMP_A_DPTR
                     )
                  )
               then
                  pcsel <= '1';
               else
                  pcsel <= '0';
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Program Counter incremented buffer
   --------------------------------------------------------------------
   pc_inc_proc:
   --------------------------------------------------------------------
      process (pc)
      begin
         pc_inc <= pc + '1';
      end process;
   
   
   --------------------------------------------------------------------
   -- Program Counter added buffer
   --------------------------------------------------------------------
   pc_add_hand :
   --------------------------------------------------------------------
      process (pc, accreg)
      begin
         pc_add <= pc + accreg;
      end process;
   
   
   --------------------------------------------------------------------
   -- Program Counter Relative added buffer
   --------------------------------------------------------------------
   pc_rel_hand :
   --------------------------------------------------------------------
      process (pc, rel)
         variable pc_u2 : SIGNED (16 downto 0);
      begin
         pc_u2  := SIGNED('0'&pc) + SIGNED(rel);
         pc_rel <= STD_LOGIC_VECTOR(pc_u2(15 downto 0));
      end process;
   
   
   --------------------------------------------------------------------
   -- Program Counter Register
   --------------------------------------------------------------------
   pc_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               pc <= "0000000000000000";
            else
            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- Special function register write
               ----------------------------------
               if pcrele='1' then     -- PC=PC+rel
                  pc <= pc_rel;
               elsif dpadde='1' then  -- PC=DPTR+A
                  pc <= dp_add;
               elsif buffsel='1' then  -- PC=Buffer
                  pc <= addrbuff;
               elsif pcince='1' then  -- PC=PC+1
                  pc <= pc_inc;
               end if;