📄 memctrl.vhd
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--*******************************************************************--
-- Copyright (c) 1999-2001 Evatronix SA --
--*******************************************************************--
-- Please review the terms of the license agreement before using --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you --
-- inadvertently received an unauthorized copy. --
--*******************************************************************--
-----------------------------------------------------------------------
-- Project name : C8051
-- Project description : C8051 Microcontroller Unit
--
-- File name : MEMCTRL.VHD
-- File contents : Entity MEMORY_CONTROL
-- Architecture RTL of MEMORY_CONTROL
-- Purpose : External data memory control
-- External program memory control
-- External I/O devices control
--
-- Destination library : C8051_LIB
-- Dependencies : C8051_LIB.Utility
-- IEEE.STD_LOGIC_1164
-- IEEE.STD_LOGIC_UNSIGNED
-- IEEE.STD_LOGIC_ARITH
--
-- Design Engineer : M.B. D.K.
-- Quality Engineer : M.B.
-- Version : 3.01.E00
-- Last modification : 2001-10-01
-----------------------------------------------------------------------
--*******************************************************************--
-- Modifications with respect to Version 3.00.E00:
-- 3.01.E00 :
-- 2001-10-01 : added debugstepff, debugmode, flushff OCI ports
-- 2001-10-01 : added flushff_write_proc
--*******************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED."+";
use IEEE.STD_LOGIC_ARITH.ALL;
library C8051_LIB;
use C8051_LIB.UTILITY.all;
--*******************************************************************--
entity MEMORY_CONTROL is
port (
-- Control signals inputs
clk : in STD_LOGIC; -- Global clock input
rst : in STD_LOGIC; -- Global reset input
ea : in STD_LOGIC; -- External Access input
-- CPU input signals
instr : in STD_LOGIC_VECTOR(7 downto 0);
cycle : in INTEGER range 1 to 8;
phase : in INTEGER range 1 to 6;
codefetche : in STD_LOGIC; -- Opcode fetch enable
datafetche : in STD_LOGIC; -- Data fetch enable
intcall : in STD_LOGIC; -- Interrupt call routine
pcince : in STD_LOGIC;
-- ALU input signals
accreg : in STD_LOGIC_VECTOR(7 downto 0);
bitvalue : in STD_LOGIC;
cdjump : in STD_LOGIC;
cyflag : in STD_LOGIC;
-- ISR input signals
intvect : in STD_LOGIC_VECTOR(2 downto 0);
-- Ports input signals
p2reg : in STD_LOGIC_VECTOR(7 downto 0);
-- OCI control signals
debugstepff : in STD_LOGIC;
debugmode : in STD_LOGIC;
flushff : out STD_LOGIC;
-- Internal Data Memory input
ramdatai : in STD_LOGIC_VECTOR(7 downto 0);
-- CPU output signals (int/ext ROM mux)
intromacs : out STD_LOGIC; -- Internal ROM access
-- RAM_SFR Control outputs
pclreg : out STD_LOGIC_VECTOR(7 downto 0);
pchreg : out STD_LOGIC_VECTOR(7 downto 0);
-- Memory interface
memdatai : in STD_LOGIC_VECTOR( 7 downto 0);--int/extROM
memaddr : out STD_LOGIC_VECTOR(15 downto 0);--int/extROM
memwr : out STD_LOGIC; -- Memory write enable
memrd : out STD_LOGIC; -- Memory read enable
memp0acs : out STD_LOGIC; -- External memory accsess P0
memp2acs : out STD_LOGIC; -- External memory accsess P2
addrdatasel : out STD_LOGIC; -- Address/Data bus select
romoe : out STD_LOGIC; -- Int. program memory enable
psen : out STD_LOGIC; -- Ext. Program Store Enable
ale : out STD_LOGIC; -- Ext. Address Latch Enable
-- Special function register interface
sfrdatai : in STD_LOGIC_VECTOR(7 downto 0);
sfrdatamcu : out STD_LOGIC_VECTOR(7 downto 0);
sfraddr : in STD_LOGIC_VECTOR(6 downto 0);
sfrwe : in STD_LOGIC
);
end MEMORY_CONTROL;
--*******************************************************************--
architecture RTL of MEMORY_CONTROL is
-----------------------------------------------------------------
-- Registers
-----------------------------------------------------------------
-- Program Counter register
signal pc : STD_LOGIC_VECTOR(15 downto 0);
signal pc_inc : STD_LOGIC_VECTOR(15 downto 0);
signal pc_add : STD_LOGIC_VECTOR(15 downto 0);
signal pc_rel : STD_LOGIC_VECTOR(15 downto 0);
-- Data Pointer registers
signal dptr : STD_LOGIC_VECTOR(15 downto 0);
signal dp_inc : STD_LOGIC_VECTOR(15 downto 0);
signal dp_add : STD_LOGIC_VECTOR(15 downto 0);
-- Address Buffer register
signal addrbuff : STD_LOGIC_VECTOR(15 downto 0);
signal memaddrbuff: STD_LOGIC_VECTOR(7 downto 0);
signal mem_addr : STD_LOGIC_VECTOR(15 downto 0);
-- Realtive address register
signal rel : STD_LOGIC_VECTOR( 7 downto 0);
-----------------------------------------------------------------
-- Control signals
-----------------------------------------------------------------
signal pcrele : STD_LOGIC; -- PC + REL count enable
-----------------------------------------------------------------
-- Data Pointer control signals
-----------------------------------------------------------------
signal dpince : STD_LOGIC; -- DPTR increment enable
signal dpadde : STD_LOGIC; -- DPTR + A count enable
signal dplwe : STD_LOGIC; -- DPTR low byte write enable
signal dphwe : STD_LOGIC; -- DPTR high byte write enable
-----------------------------------------------------------------
-- Address Buffer control signals
-----------------------------------------------------------------
signal membufflwe : STD_LOGIC; -- Memory to Buffer low write en.
signal membuffhwe : STD_LOGIC; -- Memory to Buffer high write en.
signal rambufflwe : STD_LOGIC; -- RAM to Buffer low write en.
signal rambuffhwe : STD_LOGIC; -- RAM to Buffer high write en.
signal instrbuffwe: STD_LOGIC; -- Instr. to Buffer high write en.
-----------------------------------------------------------------
-- Memory Address control signals
-----------------------------------------------------------------
signal pcaddsel : STD_LOGIC; -- PC + A count enable
signal dpaddsel : STD_LOGIC; -- DPTR + A count enable
signal pcsel : STD_LOGIC; -- PC select
signal dpsel : STD_LOGIC; -- DPTR select
signal risel : STD_LOGIC; -- Ri select
signal buffsel : STD_LOGIC; -- Buffer select
signal intromsel : STD_LOGIC; -- Internal ROM access
signal rom_oe : STD_LOGIC; -- Internal ROM enable
-----------------------------------------------------------------
-- Relative Address control signals
-----------------------------------------------------------------
signal relwe : STD_LOGIC; -- Rel register write enable
-----------------------------------------------------------------
-- Address write selector
-----------------------------------------------------------------
signal addr_sel : STD_LOGIC_VECTOR(5 downto 0);
-----------------------------------------------------------------
-- Address check
-----------------------------------------------------------------
signal addr_chk : STD_LOGIC;
-----------------------------------------------------------------
-- External memory access via port 2
-----------------------------------------------------------------
signal memp2acso : STD_LOGIC;
begin
--------------------------------------------------------------------
-- Program counter register low byte output
--------------------------------------------------------------------
pclreg_drv:
--------------------------------------------------------------------
pclreg <=
pc(7 downto 0);
--------------------------------------------------------------------
-- Program counter register high byte output
--------------------------------------------------------------------
pchreg_drv:
--------------------------------------------------------------------
pchreg <=
pc(15 downto 8);
--------------------------------------------------------------------
-- Memory address register output
--------------------------------------------------------------------
memaddr_drv:
--------------------------------------------------------------------
memaddr <= mem_addr;
--------------------------------------------------------------------
-- Internal program memory enable
-- registered output
-- high active
--------------------------------------------------------------------
romoe_drv:
--------------------------------------------------------------------
romoe <= rom_oe;
--------------------------------------------------------------------
-- Internal ROM access flip-flop output
--------------------------------------------------------------------
intromacs_drv :
--------------------------------------------------------------------
intromacs <= intromsel;
--------------------------------------------------------------------
-- External memory accsess via Port 2
-- registered output
-- high active
--------------------------------------------------------------------
memp2acs_drv:
--------------------------------------------------------------------
memp2acs <= memp2acso;
--------------------------------------------------------------------
-- PC + REL count enable
-- PC=PC+REL
-- MEMADDR=PC+REL
--------------------------------------------------------------------
pcrele_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
pcrele <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
if cycle=3 and phase=4 then
if (instr=SJMP ) or
(instr=JZ and accreg="00000000") or
(instr=JNZ and not (accreg="00000000")) or
(instr=JC and cyflag='1') or
(instr=JNC and cyflag='0') or
(instr=JB_BIT and bitvalue='1') or
(instr=JNB_BIT and bitvalue='0') or
(instr=JBC_BIT and bitvalue='1') or
(instr=CJNE_A_ADDR and cdjump='1') or
(instr=CJNE_A_N and cdjump='1') or
(instr=CJNE_R0_N and cdjump='1') or
(instr=CJNE_R1_N and cdjump='1') or
(instr=CJNE_R2_N and cdjump='1') or
(instr=CJNE_R3_N and cdjump='1') or
(instr=CJNE_R4_N and cdjump='1') or
(instr=CJNE_R5_N and cdjump='1') or
(instr=CJNE_R6_N and cdjump='1') or
(instr=CJNE_R7_N and cdjump='1') or
(instr=CJNE_IR0_N and cdjump='1') or
(instr=CJNE_IR1_N and cdjump='1') or
(instr=DJNZ_R0 and cdjump='1') or
(instr=DJNZ_R1 and cdjump='1') or
(instr=DJNZ_R2 and cdjump='1') or
(instr=DJNZ_R3 and cdjump='1') or
(instr=DJNZ_R4 and cdjump='1') or
(instr=DJNZ_R5 and cdjump='1') or
(instr=DJNZ_R6 and cdjump='1') or
(instr=DJNZ_R7 and cdjump='1') or
(instr=DJNZ_ADDR and cdjump='1')
then
pcrele <= '1';
else
pcrele <= '0';
end if;
else
pcrele <= '0';
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- Buffer to PC write enable
-- Buffer to Memory Address write enable
--------------------------------------------------------------------
buffsel_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
buffsel <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
if (instr=ACALL_0 and cycle=2 and phase=5) or
(instr=ACALL_1 and cycle=2 and phase=5) or
(instr=ACALL_2 and cycle=2 and phase=5) or
(instr=ACALL_3 and cycle=2 and phase=5) or
(instr=ACALL_4 and cycle=2 and phase=5) or
(instr=ACALL_5 and cycle=2 and phase=5) or
(instr=ACALL_6 and cycle=2 and phase=5) or
(instr=ACALL_7 and cycle=2 and phase=5) or
(instr=LCALL and cycle=3 and phase=5) or
(instr=RET and cycle=3 and phase=5) or
(instr=RETI and cycle=3 and phase=5) or
(instr=AJMP_0 and cycle=3 and phase=5) or
(instr=AJMP_1 and cycle=3 and phase=5) or
(instr=AJMP_2 and cycle=3 and phase=5) or
(instr=AJMP_3 and cycle=3 and phase=5) or
(instr=AJMP_4 and cycle=3 and phase=5) or
(instr=AJMP_5 and cycle=3 and phase=5) or
(instr=AJMP_6 and cycle=3 and phase=5) or
(instr=AJMP_7 and cycle=3 and phase=5) or
(instr=LJMP and cycle=3 and phase=5)
then
buffsel <= '1';
else
buffsel <= '0';
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- DPTR + A count enable
-- PC=DPTR+A
--------------------------------------------------------------------
dpadde_hand:
--------------------------------------------------------------------
dpadde <=
'1' when (instr=JMP_A_DPTR and cycle=1 and phase=6) else
'0';
--------------------------------------------------------------------
-- PC + A count enable
-- MEMADDR=PC+A
--------------------------------------------------------------------
pcaddsel_hand:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
pcaddsel <= '0';
else
-------------------------------------
-- Synchronous write
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