📄 utility.vhd
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--*******************************************************************--
-- Copyright (c) 1999-2001 Evatronix SA --
--*******************************************************************--
-- Please review the terms of the license agreement before using --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you --
-- inadvertently received an unauthorized copy. --
--*******************************************************************--
-----------------------------------------------------------------------
-- Project name : C8051
-- Project description : C8051 Microcontroller Unit
--
-- File name : UTILITY.VHD
-- File contents : Package UTILITY
-- Purpose : Special Function Register description
-- Special Function Register locations
-- Special Function Register reset values
-- Interrupt Vector locations
--
-- Destination library : C8051_LIB
-- Dependencies : C8051_LIB.Utility
-- IEEE.STD_LOGIC_1164
--
-- Design Engineer : M.B. D.K.
-- Quality Engineer : M.B.
-- Version : 3.01.E00
-- Last modification : 2001-10-01
-----------------------------------------------------------------------
--*******************************************************************--
-- Modifications with respect to Version 3.00.E00:
--*******************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--*******************************************************************--
package UTILITY IS
--------------------------------------------------------------------
-- Special Function Register description
--------------------------------------------------------------------
-- Register : ID : RV : Description
-- p0 : 80h : FFh : Port 0 register
-- sp : 81h : 07h : Stack Pointer
-- dpl : 82h : 00h : Data Pointer Low
-- dph : 83h : 00h : Data Pointer High
-- pcon : 87h : 7Fh : Power Control Register -- 0XXX XXXXB
-- tcon : 88h : 00h : Timer Control Register
-- tmod : 89h : 00h : Timer Mode Control
-- tl0 : 8Ah : 00h : Timer 0 low byte counter
-- tl1 : 8Bh : 00h : Timer 1 low byte counter
-- th0 : 8Ch : 00h : Timer 0 high byte counter
-- th1 : 8Dh : 00h : Timer 1 high byte counter
-- p1 : 90h : FFh : Port 1 register
-- scon : 98h : 00h : Serial Port Control Register
-- sbuf : 99h : 00h : Serial Port Buffer Register -- ???? ????B
-- p2 : A0h : FFh : Port 2 register
-- ie : A8h : 60h : Interrupt Enable Register -- 0XX0 0000B
-- p3 : B0h : FFh : Port 3 register
-- ip : B8h : E0h : Interrupt Priority Register -- XXX0 0000B
-- psw : D0h : 00h : Program Status Word
-- acc : E0h : 00h : Accumulator
-- b : F0h : 00h : Register B
--------------------------------------------------------------------
-----------------------------------------------------------------
-- Special Function Register locations and reset values
-----------------------------------------------------------------
-- Register : ID : RV : Description
-- p0 : 80h : FFh : Port 0 register
constant P0_ID : STD_LOGIC_VECTOR(6 downto 0) := "0000000";
constant P0_RV : STD_LOGIC_VECTOR(7 downto 0) := "11111111";
-- sp : 81h : 07h : Stack Pointer
constant SP_ID : STD_LOGIC_VECTOR(6 downto 0) := "0000001";
constant SP_RV : STD_LOGIC_VECTOR(7 downto 0) := "00000111";
-- dpl : 82h : 00h : Data Pointer Low
constant DPL_ID : STD_LOGIC_VECTOR(6 downto 0) := "0000010";
constant DPL_RV : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- dph : 83h : 00h : Data Pointer High
constant DPH_ID : STD_LOGIC_VECTOR(6 downto 0) := "0000011";
constant DPH_RV : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- pcon : 87h : 7Fh : Power Control Register -- 0XXX XXXXB
constant PCON_ID : STD_LOGIC_VECTOR(6 downto 0) := "0000111";
constant PCON_RV : STD_LOGIC_VECTOR(7 downto 0) := "01111111";
-- tcon : 88h : 00h : Port 1 register
constant TCON_ID : STD_LOGIC_VECTOR(6 downto 0) := "0001000";
constant TCON_RV : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- tmod : 89h : 00h : Port 1 register direction
constant TMOD_ID : STD_LOGIC_VECTOR(6 downto 0) := "0001001";
constant TMOD_RV : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- tl0 : 8Ah : 00h : Timer 0 low byte counter
constant TL0_ID : STD_LOGIC_VECTOR(6 downto 0) := "0001010";
constant TL0_RV : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- tl1 : 8Bh : 00h : Timer 1 low byte counter
constant TL1_ID : STD_LOGIC_VECTOR(6 downto 0) := "0001011";
constant TL1_RV : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- th0 : 8Ch : 00h : Timer 0 high byte counter
constant TH0_ID : STD_LOGIC_VECTOR(6 downto 0) := "0001100";
constant TH0_RV : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- th1 : 8Dh : 00h : Timer 2 high byte counter
constant TH1_ID : STD_LOGIC_VECTOR(6 downto 0) := "0001101";
constant TH1_RV : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- p1 : 90h : FFh : Port 1 register
constant P1_ID : STD_LOGIC_VECTOR(6 downto 0) := "0010000";
constant P1_RV : STD_LOGIC_VECTOR(7 downto 0) := "11111111";
-- scon : 98h : 00h : Serial Port Control Register
constant SCON_ID : STD_LOGIC_VECTOR(6 downto 0) := "0011000";
constant SCON_RV : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- sbuf : 99h : 00h : Serial Port Buffer Register--???? ????B
constant SBUF_ID : STD_LOGIC_VECTOR(6 downto 0) := "0011001";
constant SBUF_RV : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- p2 : A0h : FFh : Port 2 register
constant P2_ID : STD_LOGIC_VECTOR(6 downto 0) := "0100000";
constant P2_RV : STD_LOGIC_VECTOR(7 downto 0) := "11111111";
-- ie : A8h : 60h : Interrupt Enable Register -- 0XX0 0000B
constant IE_ID : STD_LOGIC_VECTOR(6 downto 0) := "0101000";
constant IE_RV : STD_LOGIC_VECTOR(7 downto 0) := "01100000";
-- p3 : B0h : FFh : Port 3 register
constant P3_ID : STD_LOGIC_VECTOR(6 downto 0) := "0110000";
constant P3_RV : STD_LOGIC_VECTOR(7 downto 0) := "11111111";
-- ip : B8h : E0h : Interrupt Priority Registe-- XXX0 0000B
constant IP_ID : STD_LOGIC_VECTOR(6 downto 0) := "0111000";
constant IP_RV : STD_LOGIC_VECTOR(7 downto 0) := "11100000";
-- psw : D0h : 00h : Program Status Word
constant PSW_ID : STD_LOGIC_VECTOR(6 downto 0) := "1010000";
constant PSW_RV : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- acc : E0h : 00h : Accumulator
constant ACC_ID : STD_LOGIC_VECTOR(6 downto 0) := "1100000";
constant ACC_RV : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-- b : F0h : 00h : Register B
constant B_ID : STD_LOGIC_VECTOR(6 downto 0) := "1110000";
constant B_RV : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
-------------------------------------------------------------------
-- Instruction Mnemonics
-------------------------------------------------------------------
-- 00H - 0Fh
constant NOP : STD_LOGIC_VECTOR(7 downto 0) := "00000000";
constant AJMP_0 : STD_LOGIC_VECTOR(7 downto 0) := "00000001";
constant LJMP : STD_LOGIC_VECTOR(7 downto 0) := "00000010";
constant RR_A : STD_LOGIC_VECTOR(7 downto 0) := "00000011";
constant INC_A : STD_LOGIC_VECTOR(7 downto 0) := "00000100";
constant INC_ADDR : STD_LOGIC_VECTOR(7 downto 0) := "00000101";
constant INC_IR0 : STD_LOGIC_VECTOR(7 downto 0) := "00000110";
constant INC_IR1 : STD_LOGIC_VECTOR(7 downto 0) := "00000111";
constant INC_R0 : STD_LOGIC_VECTOR(7 downto 0) := "00001000";
constant INC_R1 : STD_LOGIC_VECTOR(7 downto 0) := "00001001";
constant INC_R2 : STD_LOGIC_VECTOR(7 downto 0) := "00001010";
constant INC_R3 : STD_LOGIC_VECTOR(7 downto 0) := "00001011";
constant INC_R4 : STD_LOGIC_VECTOR(7 downto 0) := "00001100";
constant INC_R5 : STD_LOGIC_VECTOR(7 downto 0) := "00001101";
constant INC_R6 : STD_LOGIC_VECTOR(7 downto 0) := "00001110";
constant INC_R7 : STD_LOGIC_VECTOR(7 downto 0) := "00001111";
-- 10H - 1Fh
constant JBC_BIT : STD_LOGIC_VECTOR(7 downto 0) := "00010000";
constant ACALL_0 : STD_LOGIC_VECTOR(7 downto 0) := "00010001";
constant LCALL : STD_LOGIC_VECTOR(7 downto 0) := "00010010";
constant RRC_A : STD_LOGIC_VECTOR(7 downto 0) := "00010011";
constant DEC_A : STD_LOGIC_VECTOR(7 downto 0) := "00010100";
constant DEC_ADDR : STD_LOGIC_VECTOR(7 downto 0) := "00010101";
constant DEC_IR0 : STD_LOGIC_VECTOR(7 downto 0) := "00010110";
constant DEC_IR1 : STD_LOGIC_VECTOR(7 downto 0) := "00010111";
constant DEC_R0 : STD_LOGIC_VECTOR(7 downto 0) := "00011000";
constant DEC_R1 : STD_LOGIC_VECTOR(7 downto 0) := "00011001";
constant DEC_R2 : STD_LOGIC_VECTOR(7 downto 0) := "00011010";
constant DEC_R3 : STD_LOGIC_VECTOR(7 downto 0) := "00011011";
constant DEC_R4 : STD_LOGIC_VECTOR(7 downto 0) := "00011100";
constant DEC_R5 : STD_LOGIC_VECTOR(7 downto 0) := "00011101";
constant DEC_R6 : STD_LOGIC_VECTOR(7 downto 0) := "00011110";
constant DEC_R7 : STD_LOGIC_VECTOR(7 downto 0) := "00011111";
-- 20H - 2Fh
constant JB_BIT : STD_LOGIC_VECTOR(7 downto 0) := "00100000";
constant AJMP_1 : STD_LOGIC_VECTOR(7 downto 0) := "00100001";
constant RET : STD_LOGIC_VECTOR(7 downto 0) := "00100010";
constant RL_A : STD_LOGIC_VECTOR(7 downto 0) := "00100011";
constant ADD_N : STD_LOGIC_VECTOR(7 downto 0) := "00100100";
constant ADD_ADDR : STD_LOGIC_VECTOR(7 downto 0) := "00100101";
constant ADD_IR0 : STD_LOGIC_VECTOR(7 downto 0) := "00100110";
constant ADD_IR1 : STD_LOGIC_VECTOR(7 downto 0) := "00100111";
constant ADD_R0 : STD_LOGIC_VECTOR(7 downto 0) := "00101000";
constant ADD_R1 : STD_LOGIC_VECTOR(7 downto 0) := "00101001";
constant ADD_R2 : STD_LOGIC_VECTOR(7 downto 0) := "00101010";
constant ADD_R3 : STD_LOGIC_VECTOR(7 downto 0) := "00101011";
constant ADD_R4 : STD_LOGIC_VECTOR(7 downto 0) := "00101100";
constant ADD_R5 : STD_LOGIC_VECTOR(7 downto 0) := "00101101";
constant ADD_R6 : STD_LOGIC_VECTOR(7 downto 0) := "00101110";
constant ADD_R7 : STD_LOGIC_VECTOR(7 downto 0) := "00101111";
-- 30H - 3Fh
constant JNB_BIT : STD_LOGIC_VECTOR(7 downto 0) := "00110000";
constant ACALL_1 : STD_LOGIC_VECTOR(7 downto 0) := "00110001";
constant RETI : STD_LOGIC_VECTOR(7 downto 0) := "00110010";
constant RLC_A : STD_LOGIC_VECTOR(7 downto 0) := "00110011";
constant ADDC_N : STD_LOGIC_VECTOR(7 downto 0) := "00110100";
constant ADDC_ADDR : STD_LOGIC_VECTOR(7 downto 0) := "00110101";
constant ADDC_IR0 : STD_LOGIC_VECTOR(7 downto 0) := "00110110";
constant ADDC_IR1 : STD_LOGIC_VECTOR(7 downto 0) := "00110111";
constant ADDC_R0 : STD_LOGIC_VECTOR(7 downto 0) := "00111000";
constant ADDC_R1 : STD_LOGIC_VECTOR(7 downto 0) := "00111001";
constant ADDC_R2 : STD_LOGIC_VECTOR(7 downto 0) := "00111010";
constant ADDC_R3 : STD_LOGIC_VECTOR(7 downto 0) := "00111011";
constant ADDC_R4 : STD_LOGIC_VECTOR(7 downto 0) := "00111100";
constant ADDC_R5 : STD_LOGIC_VECTOR(7 downto 0) := "00111101";
constant ADDC_R6 : STD_LOGIC_VECTOR(7 downto 0) := "00111110";
constant ADDC_R7 : STD_LOGIC_VECTOR(7 downto 0) := "00111111";
-- 40H - 4Fh
constant JC : STD_LOGIC_VECTOR(7 downto 0) := "01000000";
constant AJMP_2 : STD_LOGIC_VECTOR(7 downto 0) := "01000001";
constant ORL_ADDR_A : STD_LOGIC_VECTOR(7 downto 0) := "01000010";
constant ORL_ADDR_N : STD_LOGIC_VECTOR(7 downto 0) := "01000011";
constant ORL_A_N : STD_LOGIC_VECTOR(7 downto 0) := "01000100";
constant ORL_A_ADDR : STD_LOGIC_VECTOR(7 downto 0) := "01000101";
constant ORL_A_IR0 : STD_LOGIC_VECTOR(7 downto 0) := "01000110";
constant ORL_A_IR1 : STD_LOGIC_VECTOR(7 downto 0) := "01000111";
constant ORL_A_R0 : STD_LOGIC_VECTOR(7 downto 0) := "01001000";
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