timer.vhd

51单片机内核vhdl实现 xilinx平台的

               -- Synchronous write
               -------------------------------------
               -- t1 input flip-flop
               ----------------------------------
               t1_ff0 <= t1;
               
               if (cycle=2 or cycle=4 or cycle=6 or cycle=8) and
                  (phase=3)
               then   -- s5p2 then 
                  ----------------------------------
                  -- Falling edge detection
                  ----------------------------------
                  if t1_ff0='0' and t1_ff='1' then
                     t1_fall <= '1';
                  else
                     t1_fall <= '0';
                  end if;
                  ----------------------------------
                  -- t1 input flip-flop
                  ----------------------------------
                  t1_ff  <= t1_ff0;   
               end if;
            
               if (cycle=1 or cycle=3 or cycle=5 or cycle=7) and 
                  (phase=3) and
                  (t1_fall='1')
               then
                  t1_fall_clk <='1';
               else
                  t1_fall_clk <='0';
               end if;
            end if;
         end if;
      end process;
   
   --------------------------------------------------------------------
   -- Falling edge or low level detection on the external inputs int0
   -- and int1
   -- int0, int1_fall is high active during single clk period
   --------------------------------------------------------------------
   ext_int_ff_proc :
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
         
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               int0_ff  <= '0';
               int0_int <= '0';
               int1_ff  <= '0'; 
               int1_int <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- int0, int1 input flip-flops
               ---------------------------------- 
               int0_int <=int0;
               int1_int <=int1;
               
               if (cycle=2 or cycle=4 or
                   cycle=6 or cycle=8) and 
                  (phase=2)
               then 
                  ----------------------------------
                  -- int0 input flip-flops
                  ---------------------------------- 
                  int0_ff <= int0_int;
                  ----------------------------------
                  -- int1 input flip-flops
                  ---------------------------------- 
                  int1_ff <= int1_int;
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Timer 0 open gate control
   --------------------------------------------------------------------
   t0_open_hand :
   --------------------------------------------------------------------
   t0_open <= tcon(4) and (int0_ff or not tmod(3));
   
   
   --------------------------------------------------------------------
   -- Timer 1 open gate control
   --------------------------------------------------------------------
   t1_open_hand :
   --------------------------------------------------------------------
      t1_open <= tcon(6) and (int1_ff or not tmod(7));
   
   
   --------------------------------------------------------------------
   -- Timer 0 low ordered byte clock
   -- tl0_clk is high active during single clk period
   --------------------------------------------------------------------
   tl0_clk_hand :
   --------------------------------------------------------------------
      tl0_clk <=
         t0_clk      when (t0_open='1' and tmod(2)='0') else
         t0_fall_clk when (t0_open='1' and tmod(2)='1') else
         '0';
   
   
   --------------------------------------------------------------------
   -- Timer 1 low ordered byte clock
   -- tl0_clk is high active during single clk period
   --------------------------------------------------------------------
   tl1_clk_hand :
   --------------------------------------------------------------------
      tl1_clk <=
         t1_clk      when (t1_open='1' and
                           tmod(6)='0' and
                           not (t1_mode="11")
                          ) else 
         t1_fall_clk when (t1_open='1' and
                           tmod(6)='1'and
                           not (t1_mode="11")
                          ) else
         '0';
   
   
   --------------------------------------------------------------------
   -- Timer 0 high ordered byte clock
   -- th0_clk is high active during single clk period
   --------------------------------------------------------------------
   th0_clk_hand :
   --------------------------------------------------------------------
      th0_clk <=
         tl0_ov when (t0_mode="00" or t0_mode="01") else --Modes 0 or 1
         t0_clk when (tcon(6)='1' and t0_mode="11") else --Mode 3
         '0';
   
   
   --------------------------------------------------------------------
   -- Timer 1 high ordered byte clock
   -- th1_clk is high active during single clk period
   --------------------------------------------------------------------
   th1_clk_hand :
   --------------------------------------------------------------------
      th1_clk <=
         tl1_ov when (t1_mode="00" or t1_mode="01") else --Modes 0 or 1
         '0';
   
   
   --------------------------------------------------------------------
   -- Timer low 0 overflow
   -- tl0_ov is high active during single clk period
   --------------------------------------------------------------------
   tl0_ov_hand : 
      process (clk)
      begin
         if clk'event and clk='1' then         
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               tl0_flag <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if ((tl0(4 downto 0)="11111" and t0_mode="00") or
                      (tl0(7 downto 0)="11111111")) then
                  if tl0_clk = '1' then
                     tl0_flag <= '1';
                  end if;
               end if;
               if phase=2 then               
                  tl0_flag <= '0'; 
               end if;    
            end if;
         end if;
      end process;
   
      --------------------------------------------------------------------
      -- Timer low 0 overflow
      -- tl0_ov is high active during single clk period
      --------------------------------------------------------------------
      tl0_ov <=
         tl0_clk when (
                         (tl0(4 downto 0)="11111" and t0_mode="00") or
                         (tl0(7 downto 0)="11111111")
                      ) else
         '0';
   
   
   --------------------------------------------------------------------
   -- Timer low 1 overflow
   -- tl1_ov is high active during single clk period
   --------------------------------------------------------------------
   tl1_ov_proc :
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then         
               -------------------------------------
               -- Synchronous reset
               -------------------------------------
            if rst='1' then
               tl1_flag <= '0';
            else
               -------------------------------------
               -- Synchronous write
               -------------------------------------
               if tl1(7 downto 0)="11111111" and t1_mode="10" then
                  if tl1_clk = '1' then
                     tl1_flag <= '1';
                  end if;
               end if;
               if phase=2 then               
                  tl1_flag <= '0'; 
               end if;    
            end if;
         end if;
      end process;
   
   --------------------------------------------------------------------
   -- timer low 1 overflow
   --------------------------------------------------------------------
      tl1_ov <=
         tl1_clk when ((tl1(4 downto 0)="11111" and t1_mode="00") or
                          (tl1(7 downto 0)="11111111")
                      ) else
         '0';
   
   
   --------------------------------------------------------------------
   -- Timer high 0 overflow
   -- th0_ov is high active during single clk period
   --------------------------------------------------------------------
   th0_ov_proc :
      process (clk)
      begin
         if clk'event and clk='1' then         
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               th0_ov <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if th0(7 downto 0)="11111111" then
                  th0_ov <= th0_clk;
               elsif phase=2 then               
                  th0_ov <= '0'; 
               end if;    
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Timer high 0 overflow
   -- th1_ov is high active during single clk period
   -------------------------------------------------------------------- 
   th1_ov_hand : 
      process (clk)
      begin
         if clk'event and clk='1' then 
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               th1_ov <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if th1(7 downto 0)="11111111" then
                  th1_ov <= th1_clk;
               elsif phase=2 then               
                  th1_ov <= '0'; 
               end if;    
            end if;
         end if;
      end process; 
   
   
   --------------------------------------------------------------------
   -- Special Function registers read
   --------------------------------------------------------------------
   sfr_read :
   --------------------------------------------------------------------
      sfrdatatim <=
         tl0  when sfraddr=TL0_ID  else
         th0  when sfraddr=TH0_ID  else
         tl1  when sfraddr=TL1_ID  else
         th1  when sfraddr=TH1_ID  else
         tmod when sfraddr=TMOD_ID else
         tcon when sfraddr=TCON_ID else
         "--------";   
   
   end RTL;
--*******************************************************************--