timer.vhd

51单片机内核vhdl实现 xilinx平台的

                            cycle=6 or cycle=8) and
                           (phase=2)
                        then            
                           if int1_int='0' and int1_ff='1' then --falling
                              tcon(3) <= '1';
                           end if;
                        end if;
                     end if;
                  end if;
               
                  ----------------------------------
                  -- Timer 0 overflow flag TF0
                  ----------------------------------
                  if (
                        (
                           (t0_mode="00" or t0_mode="01") and 
                           (th0_ov='1')
                        ) or
                        (
                           (t0_mode="10" or t0_mode="11") and
                           (tl0_flag='1')
                        )
                     ) and
                     (
                        (cycle=2 or cycle=4 or cycle=6 or cycle=8) and 
                        (phase=2)   -- s5p2 
                     )
                  then
                     tcon(5) <= '1';
                  else
                  
                  ----------------------------------
                  -- Timer 0 interrupt acknowledge
                  ----------------------------------
                     if t0ack='1' then
                        tcon(5) <= '0';
                     end if;
                  
                  end if;
               
                  ----------------------------------
                  -- Timer 1 overflow flag TF1
                  ----------------------------------
                  if (
                        (
                           (t1_mode="00" or t1_mode="01") and 
                           (th1_ov='1')
                        ) or
                        (t1_mode="10" and tl1_flag='1'
                        ) or
                        (t0_mode="11" and th0_ov='1'
                        )
                     ) and
                     ( 
                        (cycle=2 or cycle=4 or cycle=6 or cycle=8) and 
                        (phase=2)   -- s5p2
                     )
                  then
                     tcon(7) <= '1';
                  else
                  
                  ----------------------------------
                  -- Timer 1 interrupt acknoledge
                  ----------------------------------
                     if t1ack='1' then
                        tcon(7) <= '0';
                     end if;
                  end if;   
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- tmod register
   --------------------------------------------------------------------
   tmod_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               tmod <= TMOD_RV;
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- Special function register write
               ----------------------------------
               if (sfrwe='1' and sfraddr=TMOD_ID) then
                  tmod <= sfrdatai;
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- timer register
   --------------------------------------------------------------------
   timer0_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               tl0 <= TL0_RV;
               th0 <= TH0_RV;
            else
            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- Special function register write
               ----------------------------------
               if (sfrwe='1' and sfraddr=TL0_ID) then
                  tl0 <= sfrdatai;
               end if;
               if (sfrwe='1' and sfraddr=TH0_ID) then
                  th0 <= sfrdatai;
               end if;
            
               ----------------------------------
               -- Timer 0 count/reload
               ----------------------------------
               if (t0_mode="10" and tl0_ov='1') then
                  tl0 <= th0;  -- Reload mode
               else
                  if tl0_clk='1' then               
                     tl0 <= tl0 + '1';
                  end if;
               end if;
               if th0_clk='1' then
                  th0 <= th0 + '1';
               end if;
            
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- timer 1 register
   --------------------------------------------------------------------
   timer1_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               tl1 <= TL1_RV;
               th1 <= TH1_RV;
            else
            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               ----------------------------------
               -- Special function register write
               ----------------------------------
               if (sfrwe='1' and sfraddr=TL1_ID) then
                  tl1 <= sfrdatai;
               end if;
               if (sfrwe='1' and sfraddr=TH1_ID) then
                  th1 <= sfrdatai;
               end if;
            
               ----------------------------------
               -- Timer 1 count
               ----------------------------------
               if (t1_mode="10" and tl1_ov='1') then
                  tl1 <= th1;  -- Reload mode
               else
                  if tl1_clk='1' then
                     tl1 <= tl1 + '1';
                  end if;
                  if th1_clk='1' then
                     th1 <= th1 + '1';
                  end if;
               end if;
            
            end if;
         end if;
      end process;
   
   
   
   
   --------------------------------------------------------------------
   -- Timer 0 clock
   -- t0_clk is high active during single clk period
   --------------------------------------------------------------------
   t0_clk_sel :
   --------------------------------------------------------------------
      t0_clk <=
         '1' when (
                     (cycle=1 or cycle=3 or       -- s3p1
                      cycle=5 or cycle=7) and
                     (phase=3)
                  ) else
         '0';
   
   
   --------------------------------------------------------------------
   -- Timer 1 clock
   -- t1_clk is high active during single clk period
   --------------------------------------------------------------------
   t1_clk_sel :
   --------------------------------------------------------------------
      t1_clk <= 
         '1' when (
                     (cycle=1 or cycle=3 or      -- s3p1
                      cycle=5 or cycle=7) and
                     (phase=3)
                  ) else
         '0';
   
   
   --------------------------------------------------------------------
   -- Falling edge detection on the external input t0
   -- t0_fall is high active during single clk period
   --------------------------------------------------------------------
   t0_fall_proc :
   --------------------------------------------------------------------
      process (clk)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                     
      begin
         if clk'event and clk='1' then
         
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               t0_fall <= '0';
               t0_ff   <= '0';
               t0_ff0  <= '0';
               t0_fall_clk <='0';
            else
               -------------------------------------
               -- Synchronous write
               ----------------------------------
               -- t0 input flip-flop
               ----------------------------------
               t0_ff0 <= t0;
               
               if (cycle=2 or cycle=4 or cycle=6 or cycle=8)and
                  (phase=3)
               then   -- s5p2 then 
               -------------------------------------
               -- Falling edge detection
               ----------------------------------
                  if t0_ff0='0' and t0_ff='1' then
                     t0_fall <= '1';
                  else
                     t0_fall <= '0';
                  end if;
               ----------------------------------
               -- t0 input flip-flop
               ----------------------------------
                  t0_ff  <= t0_ff0; 
               end if;
               
               if (cycle=1 or cycle=3 or cycle=5 or cycle=7) and
                  (phase=3) and
                  (t0_fall='1') 
               then
                  t0_fall_clk <='1';
               else
                  t0_fall_clk <='0';
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Falling edge detection on the external input t1
   -- t1_fall is high active during single clk period
   --------------------------------------------------------------------
   t1_fall_proc :
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
         
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               t1_fall <= '0';
               t1_ff   <= '0';
               t1_ff0  <= '0';
            else
               -------------------------------------