📄 timer.vhd
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--*******************************************************************--
-- Copyright (c) 1999-2001 Evatronix SA --
--*******************************************************************--
-- Please review the terms of the license agreement before using --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you --
-- inadvertently received an unauthorized copy. --
--*******************************************************************--
-----------------------------------------------------------------------
-- Project name : C8051
-- Project description : C8051 Microcontroller Unit
--
-- File name : TIMER.VHD
-- File contents : Entity TIMER_0_1
-- Architecture RTL of TIMER_0_1
-- Purpose : Timer/Counter 0
-- Timer/Counter 1
--
-- Destination library : C8051_LIB
-- Dependencies : C8051_LIB.UTILITY
-- IEEE.STD_LOGIC_1164
-- IEEE.STD_LOGIC_UNSIGNED
--
-- Design Engineer : M.B. A.B. D.K.
-- Quality Engineer : M.B.
-- Version : 3.00.E01
-- Last modification : 2000-05-15
-----------------------------------------------------------------------
--*******************************************************************--
-- Modifications with respect to Version 3.00.E00:
-- 3.00.E01 :
-- 2000-05-15 : falling edge detection on the external input
-- t0, t1 changed
-- 3.01.E00 :
-- 2001-10-01 : added t0_ff0 and t1_ff0 input flip-flops
-- 2001-10-01 : modifed edge detection on the int0, int1 inputs
--*******************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED."+";
library C8051_LIB;
use C8051_LIB.UTILITY.all;
--*******************************************************************--
entity TIMER_0_1 is
port (
-- Control signals inputs
clk : in STD_LOGIC; -- Global clock input
rst : in STD_LOGIC; -- Global reset input
-- CPU input signals
cycle : in INTEGER range 1 to 8;
phase : in INTEGER range 1 to 6;
-- Timers inputs
t0 : in STD_LOGIC; -- Timer 0 external input
t1 : in STD_LOGIC; -- Timer 1 external input
t0ack : in STD_LOGIC; -- Timer 0 int. acknowledge
t1ack : in STD_LOGIC; -- Timer 1 int. acknowledge
int0 : in STD_LOGIC; -- External interrupt 0 input
int1 : in STD_LOGIC; -- External interrupt 1 input
int0ack : in STD_LOGIC; -- External int0 acknowledge
int1ack : in STD_LOGIC; -- External int1 acknowledge
-- Timer interrupt flags
tf0 : out STD_LOGIC; -- Timer 0 overflow flag
tf1 : out STD_LOGIC; -- Timer 1 overflow flag
ie0 : out STD_LOGIC; -- Interrupt 0 edge detect
ie1 : out STD_LOGIC; -- Interrupt 1 edge detect
-- Timer outputs
t1ov : out STD_LOGIC; -- Timer 1 overflow output
-- Special function register interface
sfrdatai : in STD_LOGIC_VECTOR(7 downto 0);
sfrdatatim : out STD_LOGIC_VECTOR(7 downto 0);
sfraddr : in STD_LOGIC_VECTOR(6 downto 0);
sfrwe : in STD_LOGIC
);
end TIMER_0_1;
--*******************************************************************--
architecture RTL of TIMER_0_1 is
-----------------------------------------------------------------
-- Timer/Counter registers
-----------------------------------------------------------------
signal tl0 : STD_LOGIC_VECTOR(7 downto 0);
signal th0 : STD_LOGIC_VECTOR(7 downto 0);
signal tl1 : STD_LOGIC_VECTOR(7 downto 0);
signal th1 : STD_LOGIC_VECTOR(7 downto 0);
-----------------------------------------------------------------
-- Control registers
-----------------------------------------------------------------
signal tcon : STD_LOGIC_VECTOR(7 downto 0);
signal tmod : STD_LOGIC_VECTOR(7 downto 0);
-----------------------------------------------------------------
-- Timer 0 control signals
-----------------------------------------------------------------
-- External input t0 falling edge detector
signal t0_fall : STD_LOGIC; -- t0 input fall edge detector
signal t0_ff : STD_LOGIC; -- t0 input flip-flop
signal t0_ff0 : STD_LOGIC; -- t0 input flip-flop
signal t0_fall_clk:STD_LOGIC;
-- External input int0 falling edge detector
signal int0_ff : STD_LOGIC; -- int0 input flip-flop
-- Timer 0 mode
signal t0_mode : STD_LOGIC_VECTOR(1 downto 0);
-----------------------------------------------------------------
-- Timer 0 signals
-----------------------------------------------------------------
signal t0_clk : STD_LOGIC; -- Timer 0 clock
signal t0_open : STD_LOGIC; -- Timer 0 open
signal tl0_clk : STD_LOGIC; -- Timer low 0 clock
signal th0_clk : STD_LOGIC; -- Timer high 0 clock
signal tl0_ov : STD_LOGIC; -- Timer low 0 overflow
signal tl0_flag : STD_LOGIC; -- Timer low 0 overflow
signal th0_ov : STD_LOGIC; -- Timer high 0 overflow
signal int0_int : STD_LOGIC;
-----------------------------------------------------------------
-- Timer 1 control signals
-----------------------------------------------------------------
-- External input t1 falling edge detector
signal t1_fall : STD_LOGIC; -- t1 input fall edge detector
signal t1_ff : STD_LOGIC; -- t1 input flip-flop
signal t1_ff0 : STD_LOGIC; -- t1 input flip-flop
signal t1_fall_clk: STD_LOGIC;
-----------------------------------------------------------------
-- External input int1 falling edge detector
-----------------------------------------------------------------
signal int1_ff : STD_LOGIC; -- INT1 input flip-flop
-----------------------------------------------------------------
-- Timer 1 mode
-----------------------------------------------------------------
signal t1_mode : STD_LOGIC_VECTOR(1 downto 0);
-----------------------------------------------------------------
-- Timer 1 signals
-----------------------------------------------------------------
signal t1_clk : STD_LOGIC; -- Timer 1 clock
signal t1_open : STD_LOGIC; -- Timer 1 open
signal tl1_clk : STD_LOGIC; -- Timer low 1 clock
signal th1_clk : STD_LOGIC; -- Timer high 1 clock
signal tl1_ov : STD_LOGIC; -- Timer low 1 overflow
signal tl1_flag : STD_LOGIC;
signal th1_ov : STD_LOGIC; -- Timer high 1 overflow
signal int1_int : STD_LOGIC;
begin
--------------------------------------------------------------------
-- Timer 0 overflow flag
-- interrupt request flag
-- high active output
-- cleared by high on signal t0ack
--------------------------------------------------------------------
tf0_drv :
--------------------------------------------------------------------
tf0 <= tcon(5);
--------------------------------------------------------------------
-- Timer 1 overflow flag
-- interrupt request flag
-- high active output
-- cleared by high on signal t1ack
--------------------------------------------------------------------
tf1_drv :
--------------------------------------------------------------------
tf1 <= tcon(7);
--------------------------------------------------------------------
-- Interrupt 0 edge detect
-- interrupt request flag
-- high active output
--------------------------------------------------------------------
ie0_drv :
--------------------------------------------------------------------
ie0 <= tcon(1);
--------------------------------------------------------------------
-- Interrupt 1 edge detect
-- interrupt request flag
-- high active output
--------------------------------------------------------------------
ie1_drv :
--------------------------------------------------------------------
ie1 <= tcon(3);
--------------------------------------------------------------------
-- Timer 0 overflow output
-- output for serial interface
-- high active output
-- active during single clk period
--------------------------------------------------------------------
-- t0ov_drv :
--------------------------------------------------------------------
-- t0ov <= th0_ov;
--------------------------------------------------------------------
-- Timer 1 overflow output
-- output for serial interface
-- high active output
-- active during single clk period
--------------------------------------------------------------------
t1ov_drv :
--------------------------------------------------------------------
t1ov <= tl1_ov when t1_mode="10" else
th1_ov;
--------------------------------------------------------------------
-- Timer 0 mode
--------------------------------------------------------------------
t0_mode_hand :
--------------------------------------------------------------------
t0_mode <= tmod(1 downto 0);
--------------------------------------------------------------------
-- Timer 1 mode
--------------------------------------------------------------------
t1_mode_hand :
--------------------------------------------------------------------
t1_mode <= tmod(5 downto 4);
--------------------------------------------------------------------
-- tcon register
--------------------------------------------------------------------
tcon_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
tcon <= TCON_RV;
else
-------------------------------------
-- Synchronous write
-------------------------------------
----------------------------------
-- Special function register write
----------------------------------
if (sfrwe='1' and sfraddr=TCON_ID) then
tcon <= sfrdatai;
else
----------------------------------
-- Interrupt 0 edge/level detect
----------------------------------
if tcon(0) = '0' then -- Low level detect
if (cycle=2 or cycle=4 or
cycle=6 or cycle=8) and
(phase=2)
then
tcon(1) <= not int0_int;
end if;
else
if int0ack = '1' then -- clear int. request
tcon(1) <= '0';
else
if (cycle=2 or cycle=4 or
cycle=6 or cycle=8) and
(phase=2)
then
if int0_int='0' and int0_ff='1' then --falling
tcon(1) <= '1';
end if;
end if;
end if;
end if;
----------------------------------
-- Interrupt 1 edge/level detect
----------------------------------
if tcon(2) = '0' then -- Low level detect
if (cycle=2 or cycle=4 or
cycle=6 or cycle=8) and
(phase=2)
then
tcon(3) <= not int1_int;
end if;
else
if int1ack = '1' then -- clear int. request
tcon(3) <= '0';
else
if (cycle=2 or cycle=4 or
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