📄 ramsfrctrl.vhd
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MOV_ADDR_ADDR |
MOV_ADDR_IR0 | MOV_ADDR_IR1 |
MOV_ADDR_N |
MOV_IR0_ADDR | MOV_IR1_ADDR |
PUSH | POP |
XCH_ADDR |
CJNE_A_ADDR | DJNZ_ADDR
=>
ram_sfr_address <= memdatai;
when
CLR_BIT | SETB_BIT |
ANL_C_BIT | ANL_C_NBIT |
ORL_C_BIT | ORL_C_NBIT |
MOV_C_BIT | MOV_BIT_C |
CPL_BIT | JBC_BIT |
JB_BIT | JNB_BIT
=>
if memdatai(7) = '0' then
ram_sfr_address <= "0010" &
memdatai(6 downto 3);
else
ram_sfr_address <= '1' &
memdatai(6 downto 3) & "000";
end if;
when others => -- instr
null;
end case;
when others => -- phase (cycle = 1)
null;
end case;
when 2 => -- cycle
case phase is
when 1 => -- phase (cycle = 2)
case instr is
when
ACALL_0 | ACALL_1 |
ACALL_2 | ACALL_3 |
ACALL_4 | ACALL_5 |
ACALL_6 | ACALL_7 |
LCALL | RET |
RETI
=>
ram_sfr_address <= sp_nxt;
when others => -- instr
null;
end case;
when 4 => -- phase (cycle = 2)
case instr is
when
MOV_R0_ADDR | MOV_R1_ADDR |
MOV_R2_ADDR | MOV_R3_ADDR |
MOV_R4_ADDR | MOV_R5_ADDR |
MOV_R6_ADDR | MOV_R7_ADDR
=>
ram_sfr_address <="000" &
regsbank & instr(2 downto 0);
when
PUSH
=>
ram_sfr_address <= sp_nxt;
when others => -- instr
null;
end case;
when 6 => -- phase (cycle = 2)
case instr is
when
MOV_ADDR_ADDR
=>
ram_sfr_address <= memdatai;
when others => -- instr
null;
end case;
when others => -- phase
null;
end case;
when 3 => -- cycle
case phase is
when 1 => -- phase (cycle=1)
case instr is
when
MOV_IR0_ADDR | MOV_IR1_ADDR
=>
ram_sfr_address <= "000" &
regsbank & "00" & instr(0);
when others => -- instr
null;
end case;
when 2 => -- phase (cycle = 3)
case instr is
when
LCALL
=>
ram_sfr_address <= sp_nxt;
when others => -- instr
null;
end case;
when 3 => -- phase (cycle = 3)
case instr is
when
MOV_IR0_ADDR | MOV_IR1_ADDR
=>
ram_sfr_address <= ramdatai;
when others => -- instr
null;
end case;
when others => -- phase
null;
end case;
when others => -- cycle
null;
end case;
end if;
end if;
end process;
--------------------------------------------------------------------
-- data bus access for program counter low byte
--------------------------------------------------------------------
db_pclreg_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
db_pclreg <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
case cycle is
when 1 =>
case phase is
when 5 => -- phase (cycle = 1)
case instr is
when
ACALL_0 | ACALL_1 |
ACALL_2 | ACALL_3 |
ACALL_4 | ACALL_5 |
ACALL_6 | ACALL_7 =>
db_pclreg <= '1';
when others => -- instr
db_pclreg <= '0';
end case;
when others => -- phase
db_pclreg <= '0';
end case;
when 2 => -- cycle
case phase is
when 5 => -- phase (cycle = 2)
case instr is
when
LCALL =>
db_pclreg <= '1';
when others => -- instr
db_pclreg <= '0';
end case;
when others => -- phase
db_pclreg <= '0';
end case;
when others => -- cycle
db_pclreg <= '0';
end case;
end if;
end if;
end process;
--------------------------------------------------------------------
-- data bus access for program counter high byte
--------------------------------------------------------------------
db_pchreg_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
db_pchreg <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
case cycle is
when 2 => -- cycle
case phase is
when 5 => -- phase (cycle = 2)
case instr is
when
ACALL_0 | ACALL_1 |
ACALL_2 | ACALL_3 |
ACALL_4 | ACALL_5 |
ACALL_6 | ACALL_7 =>
db_pchreg <= '1';
when others => -- instr
db_pchreg <= '0';
end case;
when others => -- phase
db_pchreg <= '0';
end case;
when 3 => -- cycle
case phase is
when 5 => -- phase (cycle = 3)
case instr is
when
LCALL =>
db_pchreg <= '1';
when others => -- instr
db_pchreg <= '0';
end case;
when others => -- phase
db_pchreg <= '0';
end case;
when others => -- cycle
db_pchreg <= '0';
end case;
end if;
end if;
end process;
--------------------------------------------------------------------
-- RAM Data Bus Mux
--------------------------------------------------------------------
ram_datao_hand :
--------------------------------------------------------------------
ram_datao <=
pclreg when db_pclreg='1' else
pchreg when db_pchreg='1' else
sfrdatai;
--------------------------------------------------------------------
-- RAM\SFR Data Bus Mux
--------------------------------------------------------------------
data_bus_hand :
--------------------------------------------------------------------
data_bus <=
ramdatai when ram_oe='1' else
sfr_bus;
--------------------------------------------------------------------
-- Special Function registers Address write
--------------------------------------------------------------------
sfr_address_hand:
--------------------------------------------------------------------
sfr_address <= ram_sfr_address(6 downto 0);
--------------------------------------------------------------------
-- Special Function Registers Mux
--------------------------------------------------------------------
sfr_bus_hand:
--------------------------------------------------------------------
sfr_bus <=
sp when (sfr_address = SP_ID) else
sfrdataalu when (sfr_address = ACC_ID or
sfr_address = B_ID or
sfr_address = PSW_ID) else
sfrdataclk when sfr_address = PCON_ID else
sfrdatamcu when (sfr_address = DPL_ID or
sfr_address = DPH_ID) else
sfrdatatim when (sfr_address = TH0_ID or
sfr_address = TL0_ID or
sfr_address = TH1_ID or
sfr_address = TL1_ID or
sfr_address = TMOD_ID or
sfr_address = TCON_ID) else
sfrdataser when (sfr_address = SCON_ID or
sfr_address = SBUF_ID) else
sfrdataisr when (sfr_address = IE_ID or
sfr_address = IP_ID) else
sfrdataports when (sfr_address = P0_ID or
sfr_address = P1_ID or
sfr_address = P2_ID or
sfr_address = P3_ID ) else
sfrdataext;
end RTL;
--*******************************************************************--
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