📄 ramsfrctrl.vhd
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then
sp_nxt <= sfrdatai;
elsif spince='1' then
sp_nxt <= sp_inc;
elsif spdece='1' then
sp_nxt <= sp_dec;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- RAM and SFR file interface
-- RAM and SFR file output enable
--------------------------------------------------------------------
ram_sfr_oe_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
ram_oe <= '0';
sfr_oe <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
case cycle is
when 1 => -- cycle
case phase is
when 2 => -- phase (cycle=1)
case instr is
when
ADD_R0 | ADD_R1 |
ADD_R2 | ADD_R3 |
ADD_R4 | ADD_R5 |
ADD_R6 | ADD_R7 |
ADD_IR0 | ADD_IR1 |
ADDC_R0 | ADDC_R1 |
ADDC_R2 | ADDC_R3 |
ADDC_R4 | ADDC_R5 |
ADDC_R6 | ADDC_R7 |
ADDC_IR0 | ADDC_IR1 |
SUBB_R0 | SUBB_R1 |
SUBB_R2 | SUBB_R3 |
SUBB_R4 | SUBB_R5 |
SUBB_R6 | SUBB_R7 |
SUBB_IR0 | SUBB_IR1 |
INC_R0 | INC_R1 |
INC_R2 | INC_R3 |
INC_R4 | INC_R5 |
INC_R6 | INC_R7 |
INC_IR0 | INC_IR1 |
DEC_R0 | DEC_R1 |
DEC_R2 | DEC_R3 |
DEC_R4 | DEC_R5 |
DEC_R6 | DEC_R7 |
DEC_IR0 | DEC_IR1 |
ANL_A_R0 | ANL_A_R1 |
ANL_A_R2 | ANL_A_R3 |
ANL_A_R4 | ANL_A_R5 |
ANL_A_R6 | ANL_A_R7 |
ANL_A_IR0 | ANL_A_IR1 |
ORL_A_R0 | ORL_A_R1 |
ORL_A_R2 | ORL_A_R3 |
ORL_A_R4 | ORL_A_R5 |
ORL_A_R6 | ORL_A_R7 |
ORL_A_IR0 | ORL_A_IR1 |
XRL_A_R0 | XRL_A_R1 |
XRL_A_R2 | XRL_A_R3 |
XRL_A_R4 | XRL_A_R5 |
XRL_A_R6 | XRL_A_R7 |
XRL_A_IR0 | XRL_A_IR1 |
MOV_A_R0 | MOV_A_R1 |
MOV_A_R2 | MOV_A_R3 |
MOV_A_R4 | MOV_A_R5 |
MOV_A_R6 | MOV_A_R7 |
MOV_A_IR0 | MOV_A_IR1 |
MOV_ADDR_R0 | MOV_ADDR_R1 |
MOV_ADDR_R2 | MOV_ADDR_R3 |
MOV_ADDR_R4 | MOV_ADDR_R5 |
MOV_ADDR_R6 | MOV_ADDR_R7 |
MOV_ADDR_IR0 | MOV_ADDR_IR1 |
MOV_IR0_A | MOV_IR1_A |
MOV_IR0_N | MOV_IR1_N |
MOVX_A_IR0 | MOVX_A_IR1 |
MOVX_IR0_A | MOVX_IR1_A |
POP |
XCH_R0 | XCH_R1 |
XCH_R2 | XCH_R3 |
XCH_R4 | XCH_R5 |
XCH_R6 | XCH_R7 |
XCH_IR0 | XCH_IR1 |
XCHD_IR0 | XCHD_IR1 |
RET | RETI |
CJNE_R0_N | CJNE_R1_N |
CJNE_R2_N | CJNE_R3_N |
CJNE_R4_N | CJNE_R5_N |
CJNE_R6_N | CJNE_R7_N |
CJNE_IR0_N | CJNE_IR1_N |
DJNZ_R0 | DJNZ_R1 |
DJNZ_R2 | DJNZ_R3 |
DJNZ_R4 | DJNZ_R5 |
DJNZ_R6 | DJNZ_R7
=>
ram_oe <= '1';
sfr_oe <= '0';
when others => -- instr
ram_oe <= '0';
sfr_oe <= '0';
end case; -- instr
when 4 => -- phase (cycle=1)
case instr is
when
MOV_ADDR_IR0 | MOV_ADDR_IR1
=>
ram_oe <= '1';
sfr_oe <= '0';
when others => -- instr
ram_oe <= '0';
sfr_oe <= '0';
end case; -- instr
when 6 => -- phase (cycle = 1)
case instr is
when
ADD_ADDR | ADDC_ADDR |
SUBB_ADDR | INC_ADDR |
DEC_ADDR | ANL_A_ADDR |
ANL_ADDR_A | ANL_ADDR_N |
ORL_A_ADDR | ORL_ADDR_A |
ORL_ADDR_N | XRL_A_ADDR |
XRL_ADDR_A | XRL_ADDR_N |
MOV_A_ADDR |
MOV_R0_ADDR | MOV_R1_ADDR |
MOV_R2_ADDR | MOV_R3_ADDR |
MOV_R4_ADDR | MOV_R5_ADDR |
MOV_R6_ADDR | MOV_R7_ADDR |
MOV_ADDR_ADDR | PUSH |
MOV_IR0_ADDR | MOV_IR1_ADDR |
XCH_ADDR |
CLR_BIT | SETB_BIT |
CPL_BIT |
ANL_C_BIT | ANL_C_NBIT |
ORL_C_BIT | ORL_C_NBIT |
MOV_C_BIT | MOV_BIT_C |
JB_BIT | JNB_BIT |
JBC_BIT |
CJNE_A_ADDR | DJNZ_ADDR
=>
if memdatai(7) = '1'
then
ram_oe <= '0';
sfr_oe <= '1';
end if;
when others => -- instr
ram_oe <= '0';
sfr_oe <= '0';
end case; -- instr
when others => -- phase
ram_oe <= '0';
sfr_oe <= '0';
end case; -- phase
when 2 => -- cycle
case phase is
when 2 => -- phase (cycle = 2)
case instr is
when
ADD_ADDR | ADDC_ADDR |
SUBB_ADDR | INC_ADDR |
DEC_ADDR | ANL_A_ADDR |
ANL_ADDR_A | ANL_ADDR_N |
ORL_A_ADDR | ORL_ADDR_A |
ORL_ADDR_N | XRL_A_ADDR |
XRL_ADDR_A | XRL_ADDR_N |
MOV_A_ADDR |
MOV_R0_ADDR | MOV_R1_ADDR |
MOV_R2_ADDR | MOV_R3_ADDR |
MOV_R4_ADDR | MOV_R5_ADDR |
MOV_R6_ADDR | MOV_R7_ADDR |
MOV_ADDR_ADDR | PUSH |
MOV_IR0_ADDR | MOV_IR1_ADDR |
XCH_ADDR |
CLR_BIT | SETB_BIT |
CPL_BIT |
ANL_C_BIT | ANL_C_NBIT |
ORL_C_BIT | ORL_C_NBIT |
MOV_C_BIT | MOV_BIT_C |
JB_BIT | JNB_BIT |
JBC_BIT |
CJNE_A_ADDR | DJNZ_ADDR
=>
if ram_sfr_address(7)='0' then
ram_oe <= '1';
sfr_oe <= '0';
else
if not
(ram_sfr_address(6 downto 0)=P0_ID or
ram_sfr_address(6 downto 0)=P1_ID or
ram_sfr_address(6 downto 0)=P2_ID or
ram_sfr_address(6 downto 0)=P3_ID)
then
ram_oe <= '0';
sfr_oe <= '1';
end if;
end if;
when
ADD_IR0 | ADD_IR1 |
ADDC_IR0 | ADDC_IR1 |
SUBB_IR0 | SUBB_IR1 |
INC_IR0 | INC_IR1 |
DEC_IR0 | DEC_IR1 |
ANL_A_IR0 | ANL_A_IR1 |
ORL_A_IR0 | ORL_A_IR1 |
XRL_A_IR0 | XRL_A_IR1 |
MOV_A_IR0 | MOV_A_IR1 |
XCH_IR0 | XCH_IR1 |
XCHD_IR0 | XCHD_IR1 |
RET | RETI |
CJNE_IR0_N | CJNE_IR1_N
=>
ram_oe <= '1';
sfr_oe <= '0';
when others => -- instr
ram_oe <= '0';
sfr_oe <= '0';
end case;
when others => -- phase
ram_oe <= '0';
sfr_oe <= '0';
end case;
when 3 => -- cycle
case phase is
when 2 => -- phase (cycle=3)
case instr is
when
MOV_IR0_ADDR | MOV_IR1_ADDR
=>
ram_oe <= '1';
sfr_oe <= '0';
when others => -- instr
ram_oe <= '0';
sfr_oe <= '0';
end case;
when others => -- phase
ram_oe <= '0';
sfr_oe <= '0';
end case;
when others => -- cycle
ram_oe <= '0';
sfr_oe <= '0';
end case;
end if;
end if;
end process;
--------------------------------------------------------------------
-- RAM and SFR file interface
-- RAM and SFR write enable
--------------------------------------------------------------------
ram_sfr_we_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
ram_we <= '0';
sfr_we <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
case cycle is
when 1 =>
case phase is
when 5 => -- phase (cycle = 1)
case instr is
when
ACALL_0 | ACALL_1 |
ACALL_2 | ACALL_3 |
ACALL_4 | ACALL_5 |
ACALL_6 | ACALL_7 |
DJNZ_R0 | DJNZ_R1 |
DJNZ_R2 | DJNZ_R3 |
DJNZ_R4 | DJNZ_R5 |
DJNZ_R6 | DJNZ_R7
=>
ram_we <= '1';
sfr_we <= '0';
when others => -- instr
ram_we <= '0';
sfr_we <= '0';
end case;
when others => -- phase
ram_we <= '0';
sfr_we <= '0';
end case;
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