📄 ramsfrctrl.vhd
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--*******************************************************************--
-- Copyright (c) 1999-2001 Evatronix SA --
--*******************************************************************--
-- Please review the terms of the license agreement before using --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you --
-- inadvertently received an unauthorized copy. --
--*******************************************************************--
-----------------------------------------------------------------------
-- Project name : C8051
-- Project description : C8051 Microcontroller Unit
--
-- File name : RAMSFRCTRL.VHD
-- File contents : Entity RAM_SFR_CONTROL
-- Architecture RTL RAM_SFR_CONTROL
-- Purpose : 256B Data Memory Control Unit
-- Special Function Registers Control Unit
--
-- Destination library : C8051_LIB
-- Dependencies : C8051_LIB.Utility
-- IEEE.STD_LOGIC_1164
-- IEEE.STD_LOGIC_UNSIGNED
--
-- Design Engineer : M.B. D.K.
-- Quality Engineer : M.B.
-- Version : 3.01.E00
-- Last modification : 2001-10-01
-----------------------------------------------------------------------
--*******************************************************************--
-- Modifications with respect to Version 3.00.E00:
-- 3.00.E01 :
-- 2000-09-15 : Moved push in ram_sfr_we_write_proc: inside cycle C1P5
--*******************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED."+";
use IEEE.STD_LOGIC_UNSIGNED."-";
library C8051_LIB;
use C8051_LIB.UTILITY.all;
--*******************************************************************--
entity RAM_SFR_CONTROL is
port (
-- Global control signals inputs
clk : in STD_LOGIC; -- Global clock input
rst : in STD_LOGIC; -- Global reset input
-- CPU input signals
instr : in STD_LOGIC_VECTOR(7 downto 0);
cycle : in INTEGER range 1 to 8;
phase : in INTEGER range 1 to 6;
-- RAM and SFR input signals
regsbank : in STD_LOGIC_VECTOR(1 downto 0);
sfrdatai : in STD_LOGIC_VECTOR(7 downto 0);
-- Memory Control input signals
pclreg : in STD_LOGIC_VECTOR(7 downto 0);
pchreg : in STD_LOGIC_VECTOR(7 downto 0);
-- External/Internal ROM Memory interface
memdatai : in STD_LOGIC_VECTOR(7 downto 0);
-- Internal Data Bus
databus : out STD_LOGIC_VECTOR(7 downto 0);
-- RAM and SFR address bus
ramsfraddr : out STD_LOGIC_VECTOR(7 downto 0);
-- Data file interface
ramdatai : in STD_LOGIC_VECTOR(7 downto 0);
ramdatao : out STD_LOGIC_VECTOR(7 downto 0);
ramwe : out STD_LOGIC; -- Data file write enable
ramoe : out STD_LOGIC; -- Data file output enable
-- Special function register interface
sfrdataalu : in STD_LOGIC_VECTOR(7 downto 0);
sfrdataclk : in STD_LOGIC_VECTOR(7 downto 0);
sfrdataisr : in STD_LOGIC_VECTOR(7 downto 0);
sfrdatamcu : in STD_LOGIC_VECTOR(7 downto 0);
sfrdataports : in STD_LOGIC_VECTOR(7 downto 0);
sfrdataser : in STD_LOGIC_VECTOR(7 downto 0);
sfrdatatim : in STD_LOGIC_VECTOR(7 downto 0);
sfrdataext : in STD_LOGIC_VECTOR(7 downto 0);
sfrwe : out STD_LOGIC; -- SFR write enable
sfroe : out STD_LOGIC -- SFR output enable
);
end RAM_SFR_CONTROL;
--*******************************************************************--
architecture RTL of RAM_SFR_CONTROL is
-----------------------------------------------------------------
-- Stack Pointer Register control signals
-----------------------------------------------------------------
signal sp : STD_LOGIC_VECTOR(7 downto 0);
signal sp_inc : STD_LOGIC_VECTOR(7 downto 0);
signal sp_dec : STD_LOGIC_VECTOR(7 downto 0);
signal sp_nxt : STD_LOGIC_VECTOR(7 downto 0);
signal spince : STD_LOGIC;
signal spdece : STD_LOGIC;
-----------------------------------------------------------------
-- RAM and SFR address drivers
-----------------------------------------------------------------
signal ram_sfr_address : STD_LOGIC_VECTOR(7 downto 0);
signal sfr_address : STD_LOGIC_VECTOR(6 downto 0);
signal sfr_bus : STD_LOGIC_VECTOR(7 downto 0);
-----------------------------------------------------------------
-- RAM and SFR data drivers
-----------------------------------------------------------------
signal data_bus : STD_LOGIC_VECTOR(7 downto 0);
signal ram_datao : STD_LOGIC_VECTOR(7 downto 0);
-----------------------------------------------------------------
-- RAM and SFR control drivers
-----------------------------------------------------------------
signal ram_oe : STD_LOGIC;
signal ram_we : STD_LOGIC;
signal sfr_oe : STD_LOGIC;
signal sfr_we : STD_LOGIC;
-----------------------------------------------------------------
-- data bus access for Program Counter
-----------------------------------------------------------------
signal db_pclreg : STD_LOGIC;
signal db_pchreg : STD_LOGIC;
begin
--------------------------------------------------------------------
-- RAM and SFR data combinational multiplexer
--------------------------------------------------------------------
ramdatao_drv :
--------------------------------------------------------------------
ramdatao <= ram_datao;
--------------------------------------------------------------------
-- RAM and SFR address register
--------------------------------------------------------------------
ramsfraddr_drv :
--------------------------------------------------------------------
ramsfraddr <= ram_sfr_address;
--------------------------------------------------------------------
-- Data file interface
-- Data file output enable register
--------------------------------------------------------------------
ramoe_drv:
--------------------------------------------------------------------
ramoe <= ram_oe;
--------------------------------------------------------------------
-- Data file interface
-- Data file write enable register
--------------------------------------------------------------------
ramwe_drv:
--------------------------------------------------------------------
ramwe <= ram_we;
--------------------------------------------------------------------
-- Special function register interface
-- SFR output enable register
--------------------------------------------------------------------
sfroe_drv:
--------------------------------------------------------------------
sfroe <= sfr_oe;
--------------------------------------------------------------------
-- Special function register interface
-- SFR write enable register
--------------------------------------------------------------------
sfrwe_drv:
--------------------------------------------------------------------
sfrwe <= sfr_we;
--------------------------------------------------------------------
-- RAM and SFR data bus register
--------------------------------------------------------------------
databus_proc :
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
databus <= "00000000";
else
-------------------------------------
-- Synchronous write
-------------------------------------
if sfr_oe='1' or ram_oe='1' then
databus <= data_bus;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- Stack Pointer increment enable
--------------------------------------------------------------------
spince_hand:
--------------------------------------------------------------------
spince <=
'1' when (
(instr=ACALL_0 and cycle=1 and phase=1) or
(instr=ACALL_1 and cycle=1 and phase=1) or
(instr=ACALL_2 and cycle=1 and phase=1) or
(instr=ACALL_3 and cycle=1 and phase=1) or
(instr=ACALL_4 and cycle=1 and phase=1) or
(instr=ACALL_5 and cycle=1 and phase=1) or
(instr=ACALL_6 and cycle=1 and phase=1) or
(instr=ACALL_7 and cycle=1 and phase=1) or
(instr=PUSH and cycle=2 and phase=3) or
(instr=ACALL_0 and cycle=1 and phase=6) or
(instr=ACALL_1 and cycle=1 and phase=6) or
(instr=ACALL_2 and cycle=1 and phase=6) or
(instr=ACALL_3 and cycle=1 and phase=6) or
(instr=ACALL_4 and cycle=1 and phase=6) or
(instr=ACALL_5 and cycle=1 and phase=6) or
(instr=ACALL_6 and cycle=1 and phase=6) or
(instr=ACALL_7 and cycle=1 and phase=6) or
(instr=LCALL and cycle=1 and phase=6) or
(instr=LCALL and cycle=2 and phase=6)
) else
'0';
--------------------------------------------------------------------
-- Stack Pointer decrement enable
--------------------------------------------------------------------
spdece_hand:
--------------------------------------------------------------------
spdece <=
'1' when (
(instr=RET and cycle=1 and phase=6) or
(instr=RETI and cycle=1 and phase=6) or
(instr=POP and cycle=1 and phase=6) or
(instr=RET and cycle=2 and phase=6) or
(instr=RETI and cycle=2 and phase=6)
) else
'0';
--------------------------------------------------------------------
-- Stack Pointer increment vector
--------------------------------------------------------------------
sp_inc_hand:
--------------------------------------------------------------------
sp_inc <= sp + '1';
--------------------------------------------------------------------
-- Stack Pointer decrement vector
--------------------------------------------------------------------
sp_dec_hand:
--------------------------------------------------------------------
sp_dec <= sp - '1';
--------------------------------------------------------------------
-- Stack Pointer register
--------------------------------------------------------------------
sp_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
sp <= SP_RV;
else
-------------------------------------
-- Synchronous write
-------------------------------------
-- Special function register write
----------------------------------
if (sfr_we='1' and
ram_sfr_address(6 downto 0)=SP_ID
)
then
sp <= sfrdatai;
elsif phase=1 or phase=2 then
sp <= sp_nxt;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- Stack Pointer buffer
--------------------------------------------------------------------
sp_nxt_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
sp_nxt <= SP_RV;
else
-------------------------------------
-- Synchronous write
-------------------------------------
-- Special function register write
----------------------------------
if (sfr_we='1' and
ram_sfr_address(6 downto 0)=SP_ID
)
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