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anl_nbit <= psw(7) and not a2(7);
end case;
end if;
end if;
end process;
--------------------------------------------------------------------
-- boolean operation - C OR BIT
--------------------------------------------------------------------
orl_bit_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
orl_bit <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
case bit_nr is
when "000" =>
orl_bit <= psw(7) or a2(0);
when "001" =>
orl_bit <= psw(7) or a2(1);
when "010" =>
orl_bit <= psw(7) or a2(2);
when "011" =>
orl_bit <= psw(7) or a2(3);
when "100" =>
orl_bit <= psw(7) or a2(4);
when "101" =>
orl_bit <= psw(7) or a2(5);
when "110" =>
orl_bit <= psw(7) or a2(6);
when others => -- when "111"
orl_bit <= psw(7) or a2(7);
end case;
end if;
end if;
end process;
--------------------------------------------------------------------
-- boolean operation - C OR not BIT
--------------------------------------------------------------------
orl_nbit_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
orl_nbit <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
case bit_nr is
when "000" =>
orl_nbit <= psw(7) or not a2(0);
when "001" =>
orl_nbit <= psw(7) or not a2(1);
when "010" =>
orl_nbit <= psw(7) or not a2(2);
when "011" =>
orl_nbit <= psw(7) or not a2(3);
when "100" =>
orl_nbit <= psw(7) or not a2(4);
when "101" =>
orl_nbit <= psw(7) or not a2(5);
when "110" =>
orl_nbit <= psw(7) or not a2(6);
when others => -- when "111"
orl_nbit <= psw(7) or not a2(7);
end case;
end if;
end if;
end process;
--------------------------------------------------------------------
-- boolean operation - MOV BIT
--------------------------------------------------------------------
mov_bit_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
mov_bit <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
case bit_nr is
when "000" =>
mov_bit <= a2(0);
when "001" =>
mov_bit <= a2(1);
when "010" =>
mov_bit <= a2(2);
when "011" =>
mov_bit <= a2(3);
when "100" =>
mov_bit <= a2(4);
when "101" =>
mov_bit <= a2(5);
when "110" =>
mov_bit <= a2(6);
when others => -- when "111"
mov_bit <= a2(7);
end case;
end if;
end if;
end process;
--------------------------------------------------------------------
-- write overflow bit for multiplication instruction
--------------------------------------------------------------------
mul_ov_bit_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
mul_ov_bit <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
case cycle is
when 2 =>
case phase is
when 4 =>
if b="00000000" then
mul_ov_bit <= '0';
else
mul_ov_bit <= '1';
end if;
when others => -- phase
null;
end case;
when others => -- cycle
null;
end case;
end if;
end if;
end process;
--------------------------------------------------------------------
-- PSW register write
--------------------------------------------------------------------
psw_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
psw <= PSW_RV;
else
-------------------------------------
-- Synchronous write
-------------------------------------
-- Special function register write
----------------------------------
if (sfrwe='1' and sfraddr=PSW_ID) then
psw <= sfr_datao;
else
-------------------------------
-- PSW(7) CY FLAG WRITE
-------------------------------
case instr is
when
ADD_IR0 | ADD_IR1 |
ADD_R0 | ADD_R1 |
ADD_R2 | ADD_R3 |
ADD_R4 | ADD_R5 |
ADD_R6 | ADD_R7 |
ADDC_IR0 | ADDC_IR1 |
ADDC_R0 | ADDC_R1 |
ADDC_R2 | ADDC_R3 |
ADDC_R4 | ADDC_R5 |
ADDC_R6 | ADDC_R7 |
SUBB_IR0 | SUBB_IR1 |
SUBB_R0 | SUBB_R1 |
SUBB_R2 | SUBB_R3 |
SUBB_R4 | SUBB_R5 |
SUBB_R6 | SUBB_R7 |
RLC_A | RRC_A |
ADD_N | ADD_ADDR |
ADDC_N | ADDC_ADDR |
SUBB_N | SUBB_ADDR =>
if (cycle=2 and phase=6) then
psw(7) <= cy_bit;
end if;
when
CJNE_R0_N | CJNE_R1_N |
CJNE_R2_N | CJNE_R3_N |
CJNE_R4_N | CJNE_R5_N |
CJNE_R6_N | CJNE_R7_N |
CJNE_IR0_N | CJNE_IR1_N |
CJNE_A_ADDR | CJNE_A_N =>
if (cycle=2 and phase=6) then
psw(7) <= cy_bit;
end if;
when
DA_A =>
if (cycle=2 and phase=6) then
if cy_bit='1' then
psw(7) <= '1';
end if;
end if;
when
MUL_AB | DIV_AB | CLR_C =>
psw(7) <= '0';
when
SETB_C =>
psw(7) <= '1';
when
CPL_C =>
if (cycle=2 and phase=6) then
psw(7) <= not psw(7);
end if;
when
ANL_C_BIT =>
if (cycle=2 and phase=6) then
psw(7) <= anl_bit;
end if;
when
ANL_C_NBIT =>
if (cycle=2 and phase=6) then
psw(7) <= anl_nbit;
end if;
when
ORL_C_BIT =>
if (cycle=2 and phase=6) then
psw(7) <= orl_bit;
end if;
when
ORL_C_NBIT =>
if (cycle=2 and phase=6) then
psw(7) <= orl_nbit;
end if;
when
MOV_C_BIT =>
if (cycle=2 and phase=6) then
psw(7) <= mov_bit;
end if;
when others =>
null;
end case;
-------------------------------
-- PSW(6) AC FLAG WRITE
-------------------------------
case instr is
when
ADD_IR0 | ADD_IR1 |
ADD_R0 | ADD_R1 |
ADD_R2 | ADD_R3 |
ADD_R4 | ADD_R5 |
ADD_R6 | ADD_R7 |
ADDC_IR0 | ADDC_IR1 |
ADDC_R0 | ADDC_R1 |
ADDC_R2 | ADDC_R3 |
ADDC_R4 | ADDC_R5 |
ADDC_R6 | ADDC_R7 |
SUBB_IR0 | SUBB_IR1 |
SUBB_R0 | SUBB_R1 |
SUBB_R2 | SUBB_R3 |
SUBB_R4 | SUBB_R5 |
SUBB_R6 | SUBB_R7 |
ADD_N | ADD_ADDR |
ADDC_N | ADDC_ADDR |
SUBB_N | SUBB_ADDR =>
if (cycle=2 and phase=6) then
psw(6) <= ac_bit;
end if;
when others =>
null;
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