alu.vhd

51单片机内核vhdl实现 xilinx平台的

               
                  when 2 => -- cycle
                     case phase is
                        when 4 => -- phase (cycle=2)
                           case instr is
                              when 
                              ADD_ADDR     | ADDC_ADDR     |
                              ADD_IR0      | ADD_IR1       |
                              ADDC_IR0     | ADDC_IR1      |
                              SUBB_ADDR    | INC_ADDR      |
                              SUBB_IR0     | SUBB_IR1      |
                              INC_IR0      | INC_IR1       |
                              DEC_ADDR     | ANL_A_ADDR    |
                              DEC_IR0      | DEC_IR1       |
                              ANL_A_IR0    | ANL_A_IR1     |
                              ANL_ADDR_A   |
                              ORL_A_ADDR   | ORL_ADDR_A    |
                              ORL_A_IR0    | ORL_A_IR1     |
                              XRL_A_ADDR   | XRL_ADDR_A    |
                              XRL_A_IR0    | XRL_A_IR1     |
                              MOV_A_ADDR   | MOV_R0_ADDR   |
                              MOV_R1_ADDR  | MOV_R2_ADDR   |
                              MOV_R3_ADDR  | MOV_R4_ADDR   |
                              MOV_R5_ADDR  | MOV_R6_ADDR   |
                              MOV_R7_ADDR  | MOV_ADDR_ADDR |
                              MOV_A_IR0    | MOV_A_IR1     |
                              MOV_IR0_ADDR | MOV_IR1_ADDR  |
                              PUSH         | XCH_ADDR      |
                              XCH_IR0      | XCH_IR1       |
                              XCHD_IR0     | XCHD_IR1      | 
                              CLR_BIT      | SETB_BIT      |
                              CPL_BIT      | ANL_C_BIT     |
                              ANL_C_NBIT   | ORL_C_BIT     |
                              ORL_C_NBIT   | MOV_C_BIT     |
                              MOV_BIT_C    | JB_BIT        |
                              JNB_BIT      | JBC_BIT       |
                              CJNE_A_ADDR  | DJNZ_ADDR     =>
                                 a2 <= databus;
                           
                              when others => -- instr
                                 null;
                           end case;
                     
                        when 5 => -- phase (cycle=2)
                           case instr is
                              when 
                              XCH_R0      | XCH_R1     |
                              XCH_R2      | XCH_R3     |
                              XCH_R4      | XCH_R5     |
                              XCH_R6      | XCH_R7     |
                              XCH_ADDR    | XCH_IR0    |
                              XCH_IR1   
                              =>
                                 a2 <= acc;
                           
                              when 
                              XCHD_IR0    | XCHD_IR1   
                              =>
                                 a2(3 downto 0) <= acc(3 downto 0);                           
                           
                              when others => -- instr
                                 null;
                           end case;                            
                     
                        when 6 => -- phase (cycle=2)
                           case instr is
                              when
                              ANL_ADDR_N   | ORL_ADDR_N |
                              XRL_ADDR_N   | MOV_ADDR_N =>
                                 a2 <= memdatai;
                           
                              when others => -- instr
                                 null;
                           end case;                            
                     
                        when others => -- phase 
                           null;
                     end case;
               
                  when others => -- cycle
                     null;
               end case;
            
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- ALU operand write process
   --------------------------------------------------------------------
   op_c_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
         -------------------------------------
         -- Synchronous reset
         -------------------------------------
            if rst='1' then
               op_c <= '0';
            else            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if cycle = 1 and phase = 1 then
                  op_c <= psw(7);
               end if;
            end if;
         end if;       
      end process;
   
   
   --------------------------------------------------------------------
   -- ALU result write process
   --------------------------------------------------------------------
   b1_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               b1 <= "00000000";
            else            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               b1 <= result_b1(7 downto 0);
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- ALU result write process
   --------------------------------------------------------------------
   b2_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               b2 <= "00000000";
            else            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               b2 <= result_b2(7 downto 0);
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- ALU result write process
   --------------------------------------------------------------------
   b3_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               b3 <= "00000000";
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               b3 <= bool_res;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- b register write process
   --------------------------------------------------------------------
   b_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               b <= B_RV;
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- Special function register write
               ----------------------------------
               if (sfrwe='1' and sfraddr=B_ID) then
                  b <= sfr_datao;
               ----------------------------------
               -- b register operation write
               ----------------------------------
               else 
                  case cycle is
                     when 2 =>
                        case phase is
                           when 3 =>
                              case instr is
                                 when
                                 MUL_AB =>
                                    b <= sum(8 downto 1);
                                 when
                                 DIV_AB =>  
                                    if sum(8)='1' then -- borrow = 0
                                       b <= sum(7 downto 0);
                                    else
                                       b <= mdb(7 downto 0);
                                    end if;
                              
                                 when others =>
                                    NULL;
                              end case;
                           when others =>
                              NULL;
                        end case;
                     when others =>
                        NULL;
                  end case;           
               end if;
            
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- boolean operation - C AND BIT
   --------------------------------------------------------------------
   anl_bit_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               anl_bit <= '0';
            else            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               case bit_nr is
                  when "000" =>
                     anl_bit <= psw(7) and a2(0);
                  when "001" =>
                     anl_bit <= psw(7) and a2(1);
                  when "010" =>
                     anl_bit <= psw(7) and a2(2);
                  when "011" =>
                     anl_bit <= psw(7) and a2(3);
                  when "100" =>
                     anl_bit <= psw(7) and a2(4);
                  when "101" =>
                     anl_bit <= psw(7) and a2(5);
                  when "110" =>
                     anl_bit <= psw(7) and a2(6);
                  when others => -- when "111"
                     anl_bit <= psw(7) and a2(7);
               end case;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- boolean operation - C AND not BIT
   --------------------------------------------------------------------
   anl_nbit_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               anl_nbit <= '0';
            else            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               case bit_nr is
                  when "000" =>
                     anl_nbit <= psw(7) and not a2(0);
                  when "001" =>
                     anl_nbit <= psw(7) and not a2(1);
                  when "010" =>
                     anl_nbit <= psw(7) and not a2(2);
                  when "011" =>
                     anl_nbit <= psw(7) and not a2(3);
                  when "100" =>
                     anl_nbit <= psw(7) and not a2(4);
                  when "101" =>
                     anl_nbit <= psw(7) and not a2(5);
                  when "110" =>
                     anl_nbit <= psw(7) and not a2(6);
                  when others => -- when "111"