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XRL_A_R0 | XRL_A_R1 |
XRL_A_R2 | XRL_A_R3 |
XRL_A_R4 | XRL_A_R5 |
XRL_A_R6 | XRL_A_R7 |
XRL_A_ADDR |
XRL_A_IR0 | XRL_A_IR1 |
XRL_A_N |
CLR_A | CPL_A |
RL_A | RLC_A |
RR_A | RRC_A |
SWAP_A =>
acc <= b2;
when
MOV_A_R0 | MOV_A_R1 |
MOV_A_R2 | MOV_A_R3 |
MOV_A_R4 | MOV_A_R5 |
MOV_A_R6 | MOV_A_R7 |
MOV_A_ADDR |
MOV_A_IR0 | MOV_A_IR1 |
MOV_A_N =>
acc <= a2;
when others => -- instr
null;
end case;
when others => -- phase (cycle=2)
null;
end case;
when 3 => -- cycle
case phase is
when 5 =>
case instr is
when
MOVX_A_IR0 | MOVX_A_IR1 |
MOVX_A_IDPTR =>
acc <= memdatai;
when others => -- instr
null;
end case;
when 6 => -- phase (cycle = 2)
case instr is
when
MOVC_A_PC | MOVC_A_DPTR
=>
acc <= memdatai;
when others => -- instr
null;
end case;
when others => -- phase
null;
end case;
when others => -- cycle
null;
end case;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- ALU operand write process
--------------------------------------------------------------------
a1_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
a1 <= "00000000";
else
-------------------------------------
-- Synchronous write
-------------------------------------
case cycle is
when 1 => -- cycle
case phase is
when 2 => -- phase (cycle = 1)
case instr is
when
ADD_R0 | ADD_R1 |
ADD_R2 | ADD_R3 |
ADD_R4 | ADD_R5 |
ADD_R6 | ADD_R7 |
ADD_ADDR | ADD_IR0 |
ADD_IR1 | ADD_N |
ADDC_R0 | ADDC_R1 |
ADDC_R2 | ADDC_R3 |
ADDC_R4 | ADDC_R5 |
ADDC_R6 | ADDC_R7 |
ADDC_ADDR | ADDC_IR0 |
ADDC_IR1 | ADDC_N |
SUBB_R0 | SUBB_R1 |
SUBB_R2 | SUBB_R3 |
SUBB_R4 | SUBB_R5 |
SUBB_R6 | SUBB_R7 |
SUBB_ADDR | SUBB_IR0 |
SUBB_IR1 | SUBB_N |
ANL_A_R0 | ANL_A_R1 |
ANL_A_R2 | ANL_A_R3 |
ANL_A_R4 | ANL_A_R5 |
ANL_A_R6 | ANL_A_R7 |
ANL_A_ADDR | ANL_A_IR0 |
ANL_A_IR1 | ANL_A_N |
ANL_ADDR_A |
ORL_A_R0 | ORL_A_R1 |
ORL_A_R2 | ORL_A_R3 |
ORL_A_R4 | ORL_A_R5 |
ORL_A_R6 | ORL_A_R7 |
ORL_A_ADDR | ORL_A_IR0 |
ORL_A_IR1 | ORL_A_N |
ORL_ADDR_A |
XRL_A_R0 | XRL_A_R1 |
XRL_A_R2 | XRL_A_R3 |
XRL_A_R4 | XRL_A_R5 |
XRL_A_R6 | XRL_A_R7 |
XRL_A_ADDR | XRL_A_IR0 |
XRL_A_IR1 | XRL_A_N |
XRL_ADDR_A |
CPL_A | RL_A |
RLC_A | RR_A |
RRC_A | SWAP_A |
CJNE_A_ADDR | CJNE_A_N =>
a1 <= acc;
when others => -- instr
null;
end case;
when 4 => -- phase (cycle=1)
case instr is
when
CJNE_R0_N | CJNE_R1_N |
CJNE_R2_N | CJNE_R3_N |
CJNE_R4_N | CJNE_R5_N |
CJNE_R6_N | CJNE_R7_N =>
a1 <= databus;
when others => -- instr
null;
end case;
when others => -- phase
null;
end case;
when 2 => -- cycle
case phase is
when 4 => -- phase (cycle = 2)
case instr is
when
ANL_ADDR_N | ORL_ADDR_N |
XRL_ADDR_N |
CJNE_IR0_N | CJNE_IR1_N =>
a1 <= databus;
when others => -- instr
null;
end case;
when others => -- phase
null;
end case;
when others => -- cycle
null;
end case;
end if;
end if;
end process;
--------------------------------------------------------------------
-- ALU operand write process
--------------------------------------------------------------------
a2_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
a2 <= "00000000";
else
-------------------------------------
-- Synchronous write
-------------------------------------
case cycle is
when 1 => -- cycle
case phase is
when 4 => -- phase (cycle = 1)
case instr is
when
INC_A | DEC_A |
DA_A |
MOV_R0_A | MOV_R1_A |
MOV_R2_A | MOV_R3_A |
MOV_R4_A | MOV_R5_A |
MOV_R6_A | MOV_R7_A |
MOV_ADDR_A | MOV_IR0_A |
MOV_IR1_A =>
a2 <= acc;
when
ADD_R0 | ADD_R1 |
ADD_R2 | ADD_R3 |
ADD_R4 | ADD_R5 |
ADD_R6 | ADD_R7 |
ADDC_R0 | ADDC_R1 |
ADDC_R2 | ADDC_R3 |
ADDC_R4 | ADDC_R5 |
ADDC_R6 | ADDC_R7 |
SUBB_R0 | SUBB_R1 |
SUBB_R2 | SUBB_R3 |
SUBB_R4 | SUBB_R5 |
SUBB_R6 | SUBB_R7 |
INC_R0 | INC_R1 |
INC_R2 | INC_R3 |
INC_R4 | INC_R5 |
INC_R6 | INC_R7 |
DEC_R0 | DEC_R1 |
DEC_R2 | DEC_R3 |
DEC_R4 | DEC_R5 |
DEC_R6 | DEC_R7 |
ANL_A_R0 | ANL_A_R1 |
ANL_A_R2 | ANL_A_R3 |
ANL_A_R4 | ANL_A_R5 |
ANL_A_R6 | ANL_A_R7 |
ORL_A_R0 | ORL_A_R1 |
ORL_A_R2 | ORL_A_R3 |
ORL_A_R4 | ORL_A_R5 |
ORL_A_R6 | ORL_A_R7 |
XRL_A_R0 | XRL_A_R1 |
XRL_A_R2 | XRL_A_R3 |
XRL_A_R4 | XRL_A_R5 |
XRL_A_R6 | XRL_A_R7 |
MOV_A_R0 | MOV_A_R1 |
MOV_A_R2 | MOV_A_R3 |
MOV_A_R4 | MOV_A_R5 |
MOV_A_R6 | MOV_A_R7 |
MOV_ADDR_R0 | MOV_ADDR_R1 |
MOV_ADDR_R2 | MOV_ADDR_R3 |
MOV_ADDR_R4 | MOV_ADDR_R5 |
MOV_ADDR_R6 | MOV_ADDR_R7 |
POP | XCH_R0 |
XCH_R1 | XCH_R2 |
XCH_R3 | XCH_R4 |
XCH_R5 | XCH_R6 |
XCH_R7 |
DJNZ_R0 |
DJNZ_R1 | DJNZ_R2 |
DJNZ_R3 | DJNZ_R4 |
DJNZ_R5 | DJNZ_R6 |
DJNZ_R7 |
MOVX_IR0_A | MOVX_IR1_A |
MOVX_A_IR0 | MOVX_A_IR1 =>
a2 <= databus;
when others => -- instr
null;
end case;
when 6 => -- phase (cycle=1)
case instr is
when
ADD_N | ADDC_N |
SUBB_N | ANL_A_N |
ORL_A_N | XRL_A_N |
MOV_A_N | MOV_R0_N |
MOV_R1_N | MOV_R2_N |
MOV_R3_N | MOV_R4_N |
MOV_R5_N | MOV_R6_N |
MOV_R7_N | MOV_IR0_N |
MOV_IR1_N |
CJNE_R0_N | CJNE_R1_N |
CJNE_R2_N | CJNE_R3_N |
CJNE_R4_N | CJNE_R5_N |
CJNE_R6_N | CJNE_R7_N |
CJNE_A_N | CJNE_IR0_N |
CJNE_IR1_N =>
a2 <= memdatai;
when
MOV_ADDR_IR0 | MOV_ADDR_IR1 =>
a2 <= databus;
when others => -- instr
null;
end case;
when others => -- phase
null;
end case;
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