📄 alu.vhd
字号:
--*******************************************************************--
-- Copyright (c) 1999-2001 Evatronix SA --
--*******************************************************************--
-- Please review the terms of the license agreement before using --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you --
-- inadvertently received an unauthorized copy. --
--*******************************************************************--
-----------------------------------------------------------------------
-- Project name : C8051
-- Project description : C8051 Microcontroller Unit
--
-- File name : ALU.VHD
-- File contents : Entity ALU
-- Architecture RTL of ALU
-- Purpose : Aritmetic Logic Unit
--
-- Destination library : C8051_LIB
-- Dependencies : C8051_LIB.UTILITY
-- IEEE.STD_LOGIC_1164
-- IEEE.STD_LOGIC_UNSIGNED
--
-- Design Engineer : M.B. D.K.
-- Quality Engineer : M.B.
-- Version : 3.01.E00
-- Last modification : 2001-10-01
-----------------------------------------------------------------------
--*******************************************************************--
-- Modifications with respect to Version 3.00.E00:
--*******************************************************************--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED."+";
use IEEE.STD_LOGIC_UNSIGNED."-";
library C8051_LIB;
use C8051_LIB.UTILITY.all;
--*******************************************************************--
entity ALU is
port (
-- Global control signals inputs
clk : in STD_LOGIC; -- Global clock input
rst : in STD_LOGIC; -- Global reset input
-- CPU input signals
instr : in STD_LOGIC_VECTOR(7 downto 0);
cycle : in INTEGER range 1 to 8;
phase : in INTEGER range 1 to 6;
-- Memory interface
memdatai : in STD_LOGIC_VECTOR(7 downto 0);
-- Internal Data Bus
databus : in STD_LOGIC_VECTOR(7 downto 0);
-- ALU output signals
accreg : out STD_LOGIC_VECTOR(7 downto 0);
regsbank : out STD_LOGIC_VECTOR(1 downto 0);
bitvalue : out STD_LOGIC;
cdjump : out STD_LOGIC;
cyflag : out STD_LOGIC;
-- Special function register interface
sfraddr : in STD_LOGIC_VECTOR(6 downto 0);
sfrdatao : out STD_LOGIC_VECTOR(7 downto 0);
sfrdataalu : out STD_LOGIC_VECTOR(7 downto 0);
sfrwe : in STD_LOGIC -- SFR write enable
);
end ALU;
--*******************************************************************--
architecture RTL of ALU is
-----------------------------------------------------------------
-- Special Function Registers
-----------------------------------------------------------------
signal acc : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal b : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal psw : STD_LOGIC_VECTOR(7 DOWNTO 0);
-----------------------------------------------------------------
-- ALU operand registers
-----------------------------------------------------------------
signal a1 : STD_LOGIC_VECTOR(7 downto 0);
signal a2 : STD_LOGIC_VECTOR(7 downto 0);
signal op_c : STD_LOGIC;
-----------------------------------------------------------------
-- ALU result signals
-----------------------------------------------------------------
signal b1 : STD_LOGIC_VECTOR(7 downto 0);
signal b2 : STD_LOGIC_VECTOR(7 downto 0);
signal b3 : STD_LOGIC_VECTOR(7 downto 0);
signal result_b1 : STD_LOGIC_VECTOR(8 downto 0);
signal result_b2 : STD_LOGIC_VECTOR(8 downto 0);
-----------------------------------------------------------------
-- SFR data output bus
-----------------------------------------------------------------
signal sfr_datao : STD_LOGIC_VECTOR(7 downto 0);
-----------------------------------------------------------------
-- Bit number - for bit addressable registers
-----------------------------------------------------------------
signal bit_nr : STD_LOGIC_VECTOR(2 downto 0);
-----------------------------------------------------------------
-- PSW flags
-----------------------------------------------------------------
signal ac_flag : STD_LOGIC;
signal ov_flag : STD_LOGIC;
signal parity_flag: STD_LOGIC;
-----------------------------------------------------------------
-- PSW flag flip-flops
-----------------------------------------------------------------
signal ac_bit : STD_LOGIC;
signal ov_bit : STD_LOGIC;
signal cy_bit : STD_LOGIC;
-----------------------------------------------------------------
-- Bit operation flip-flops
-----------------------------------------------------------------
signal anl_bit : STD_LOGIC;
signal anl_nbit : STD_LOGIC;
signal orl_bit : STD_LOGIC;
signal orl_nbit : STD_LOGIC;
signal mov_bit : STD_LOGIC;
signal mul_ov_bit : STD_LOGIC;
-----------------------------------------------------------------
-- Arithmetic and logic operations result vector
-----------------------------------------------------------------
signal result : STD_LOGIC_VECTOR(8 downto 0);
-----------------------------------------------------------------
-- Boolean operation result vector
-----------------------------------------------------------------
signal bool_res : STD_LOGIC_VECTOR(7 downto 0);
-----------------------------------------------------------------
-- Multiplication / division registers
-----------------------------------------------------------------
signal mda, mdb : STD_LOGIC_VECTOR(7 downto 0);
-- combinational sum
signal sum : STD_LOGIC_VECTOR(8 downto 0);
begin
--------------------------------------------------------------------
-- ACC register output
--------------------------------------------------------------------
accreg_drv:
--------------------------------------------------------------------
accreg <= acc;
--------------------------------------------------------------------
-- Carry flag register output
--------------------------------------------------------------------
cybit_drv:
--------------------------------------------------------------------
cyflag <= psw(7);
--------------------------------------------------------------------
-- Register select bank output
--------------------------------------------------------------------
regsbank_drv:
--------------------------------------------------------------------
regsbank <= psw(4 downto 3);
--------------------------------------------------------------------
-- combinational SFR data output bus
--------------------------------------------------------------------
sfrdatao_drv:
--------------------------------------------------------------------
sfrdatao <= sfr_datao;
--------------------------------------------------------------------
-- Conditional jump control
--------------------------------------------------------------------
cdjump_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst = '1' then
cdjump <= '0';
else
-------------------------------------
-- Synchronous write
-------------------------------------
if phase = 1 then
if b1(7 downto 0)="00000000" then
cdjump <= '0';
else
cdjump <= '1';
end if;
end if;
end if;
end if;
end process;
--------------------------------------------------------------------
-- acc register write process
--------------------------------------------------------------------
acc_write_proc:
--------------------------------------------------------------------
process (clk)
begin
if clk'event and clk='1' then
-------------------------------------
-- Synchronous reset
-------------------------------------
if rst='1' then
acc <= ACC_RV;
else
-------------------------------------
-- Synchronous write
-------------------------------------
-- Special function register write
-------------------------------------
if (sfrwe='1' and sfraddr=ACC_ID) then
acc <= sfr_datao;
----------------------------------
-- ALU operation write
----------------------------------
else
case cycle is
when 2 => -- cycle
case phase is
when 4 => -- phase (cycle=2)
case instr is
when
DIV_AB | MUL_AB =>
acc <= mda;
when others => -- instr
null;
end case;
when 5 => -- phase (cycle=2)
case instr is
when
XCH_R0 | XCH_R1 |
XCH_R2 | XCH_R3 |
XCH_R4 | XCH_R5 |
XCH_R6 | XCH_R7 |
XCH_IR0 | XCH_IR1 |
XCH_ADDR =>
acc <= a2;
when
XCHD_IR0 | XCHD_IR1 =>
acc(3 downto 0) <= a2(3 downto 0);
when others => -- instr
null;
end case;
when 6 => -- phase (cycle = 2)
case instr is
when
ADD_R0 | ADD_R1 |
ADD_R2 | ADD_R3 |
ADD_R4 | ADD_R5 |
ADD_R6 | ADD_R7 |
ADD_ADDR |
ADD_IR0 | ADD_IR1 |
ADD_N |
ADDC_R0 | ADDC_R1 |
ADDC_R2 | ADDC_R3 |
ADDC_R4 | ADDC_R5 |
ADDC_R6 | ADDC_R7 |
ADDC_ADDR |
ADDC_IR0 | ADDC_IR1 |
ADDC_N |
SUBB_R0 | SUBB_R1 |
SUBB_R2 | SUBB_R3 |
SUBB_R4 | SUBB_R5 |
SUBB_R6 | SUBB_R7 |
SUBB_ADDR |
SUBB_IR0 | SUBB_IR1 |
SUBB_N |
INC_A | DEC_A =>
acc <= b1;
when
DA_A | ANL_A_R0 |
ANL_A_R1 | ANL_A_R2 |
ANL_A_R3 | ANL_A_R4 |
ANL_A_R5 | ANL_A_R6 |
ANL_A_R7 | ANL_A_ADDR |
ANL_A_IR0 | ANL_A_IR1 |
ANL_A_N |
ORL_A_R0 | ORL_A_R1 |
ORL_A_R2 | ORL_A_R3 |
ORL_A_R4 | ORL_A_R5 |
ORL_A_R6 | ORL_A_R7 |
ORL_A_ADDR |
ORL_A_IR0 | ORL_A_IR1 |
ORL_A_N |
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -