clkctrl.vhd

51单片机内核vhdl实现 xilinx平台的

--*******************************************************************--
-- Copyright (c) 1999-2001  Evatronix SA                             --
--*******************************************************************--
-- Please review the terms of the license agreement before using     --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you     --
-- inadvertently received an unauthorized copy.                      --
--*******************************************************************--

-----------------------------------------------------------------------
-- Project name         : C8051
-- Project description  : C8051 Microcontroller Unit
--
-- File name            : CLKCTRL.VHD
-- File contents        : Entity CLOCK_CONTROL
--                        Architecture RTL of CLOCK_CONTROL
-- Purpose              : Clock Control Unit
--                        Internal reset control unit
--
-- Destination library  : C8051_LIB
-- Dependencies         : C8051_LIB.UTILITY
--                        IEEE.STD_LOGIC_1164
--
-- Design Engineer      : M.B. D.K.
-- Quality Engineer     : M.B.
-- Version              : 3.01.E00
-- Last modification    : 2001-10-01
-----------------------------------------------------------------------

--*******************************************************************--
-- Modifications with respect to Version 3.00.E00:
-- 3.01.E00   :
-- 2001.10.01 : pcon_write_proc modified in case of the reset
--*******************************************************************--
library IEEE;
   use IEEE.STD_LOGIC_1164.all;
library C8051_LIB;
   use C8051_LIB.UTILITY.all;

--*******************************************************************--
   entity CLOCK_CONTROL is
      port (
           -- Control signals inputs
           clk          : in  STD_LOGIC;  -- Global clock input
           reset        : in  STD_LOGIC;  -- Hardware reset input
           
           -- CPU input signals
           cycle        : in INTEGER range 1 to 8;
           phase        : in INTEGER range 1 to 6;
           parcycle     : in STD_LOGIC;
           
           -- Internal reset driver
           rsto         : out STD_LOGIC;
           
           -- double bit rate enable
           smod         : out STD_LOGIC;
           
           -- Special function register interface
           sfrdatai     : in  STD_LOGIC_VECTOR(7 downto 0);
           sfrdataclk   : out STD_LOGIC_VECTOR(7 downto 0);
           sfraddr      : in  STD_LOGIC_VECTOR(6 downto 0);
           sfrwe        : in  STD_LOGIC
           );
   end CLOCK_CONTROL;

--*******************************************************************--

   architecture RTL of CLOCK_CONTROL is
      -----------------------------------------------------------------
      -- Power Control Register
      -----------------------------------------------------------------
      signal pcon       : STD_LOGIC_VECTOR(7 downto 0);
   
      -----------------------------------------------------------------
      -- Hardware reset detector
      ----------------------------------------------------------------- 
      signal reset_ff   : STD_LOGIC;
      signal reset_ff1  : STD_LOGIC;
      signal rst_o      : STD_LOGIC; 
   
   begin
   --------------------------------------------------------------------
   -- internal reset driver register
   --------------------------------------------------------------------
   rsto_drv :
   --------------------------------------------------------------------
      rsto <= rst_o;
   
   
   --------------------------------------------------------------------
   -- Serial Port Baud Rate Doubler Enable Register
   --------------------------------------------------------------------
   smod_drv :
   --------------------------------------------------------------------
      smod <= pcon(7);
   
   --------------------------------------------------------------------
   -- Power Control register
   --------------------------------------------------------------------
   pcon_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst_o='1' then
               pcon(7 downto 0) <= PCON_RV(7 downto 0);
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- Special function register write
               ----------------------------------
               if (sfrwe='1' and sfraddr=PCON_ID) then
                  pcon <= sfrdatai(7 downto 0);
               end if;
            end if;
         end if;
      end process; 
   
   
   --------------------------------------------------------------------
   reset_synchro_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
         
            -------------------------------------
            -- Synchronous write
            -------------------------------------
            if (parcycle='1' and 
                phase=2)
            then           -- S5P2
               reset_ff  <= reset; -- Hardware reset
            end if;
            if (parcycle='1' and 
                phase=2)
            then
               reset_ff1 <= reset_ff;
            end if;
            if (phase=2 and
                reset_ff='1' and 
                reset_ff1='1')
            then
               rst_o<='1';
            else
               if (phase=6 and
                   cycle=1 and
                   not reset_ff='1')
               then
                  rst_o<='0';
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Special Function registers read
   --------------------------------------------------------------------
   sfr_read :
   --------------------------------------------------------------------
      sfrdataclk <=                                    
         pcon when sfraddr=PCON_ID    else
         "--------";
   
   end RTL;
--*******************************************************************--