oci.vhd

51单片机内核vhdl实现 xilinx平台的

--*******************************************************************--
-- Copyright (c) 1999-2001  Evatronix SA                             --
--*******************************************************************--
-- Please review the terms of the license agreement before using     --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you     --
-- inadvertently received an unauthorized copy.                      --
--*******************************************************************--

-----------------------------------------------------------------------
-- Project name         : C8051
-- Project description  : C8051 Microcontroller Unit
--
-- File name            : OCI.VHD
-- File contents        : Entity OCI
--                        Architecture RTL of OCI
-- Purpose              : On-Chip Instrumentation
--
-- Destination library  : C8051_LIB
-- Dependencies         : C8051_LIB.UTILITY
--                        IEEE.STD_LOGIC_1164
--
-- Design Engineer      : D.K.
-- Quality Engineer     : M.B.
-- Version              : 3.01.E00
-- Last modification    : 2001-10-01
-----------------------------------------------------------------------

--*******************************************************************--
-- Modifications with respect to Version 3.00.E00:
-- 3.01.E00   :
-- 2001-01-01 : The OCI is added to this version
--*******************************************************************--

library IEEE;
   use IEEE.STD_LOGIC_1164.all;
library C8051_LIB;
   use C8051_LIB.UTILITY.all;

--*******************************************************************--
   entity OCI is
      port (
           -- Control signals inputs
           clk          : in  STD_LOGIC;  -- Global clock input
           rst          : in  STD_LOGIC;  -- Internal reset input
                      
           -- CPU input signals
           cycle        : in  INTEGER range 1 to 8;
           nrcycles     : in  INTEGER range 1 to 8;
           phase        : in  INTEGER range 1 to 6;
           codefetche   : in  STD_LOGIC;
           codefetcheff : in  STD_LOGIC;
           datafetche   : in  STD_LOGIC;
                      
           -- memory control input signal
           flushff      : in  STD_LOGIC;
           
           -- program memory input
           memdatai     : in  STD_LOGIC_VECTOR(7 downto 0);
           
           -- OCI inputs
           debugreq     : in  STD_LOGIC; -- Debug Request
           debugstep    : in  STD_LOGIC; -- Debug Step
           debugprog    : in  STD_LOGIC; -- Debugger program
           
           -- OCI outputs
           debugstepff  : out STD_LOGIC;
           debugprogff  : out STD_LOGIC;
           debugmode    : out STD_LOGIC;
           debugack     : out STD_LOGIC; -- Debug Acknowledge
           flush        : out STD_LOGIC;
           fetch        : out STD_LOGIC
           );
   end OCI;

--*******************************************************************--

   architecture RTL of OCI is
   
      -- OCI
      signal debug_mode       : STD_LOGIC;
      signal a5_instr         : STD_LOGIC;   
      signal debug_ack        : STD_LOGIC;
      signal debugstep_ff     : STD_LOGIC;
      signal debugprog_ff     : STD_LOGIC;
   
   begin
      
      debugmode <= debug_mode;
      debugack <= debug_ack;
      debugstepff <= debugstep_ff;
      debugprogff <= debugprog_ff;
      
   --------------------------------------------------------------------
   debug_mode_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               debug_mode <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if cycle=nrcycles then
                  if (  (phase=4 and debugreq='1') or -- debug request
                        (codefetcheff='1' and memdatai=UNKNOWN) or -- software breakpoint
                        a5_instr='1' -- software breakpoint
                     )
                  then
                     debug_mode <= '1';
                  elsif (phase=3 and debugreq='0') then
                     debug_mode <= '0';
                  end if;
               end if;
            end if;
         end if;
      end process;
      
   --------------------------------------------------------------------
   a5instr_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               a5_instr <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if (codefetcheff='1' and memdatai=UNKNOWN) -- software breakpoint
               then
                  a5_instr <= '1';
               elsif debugreq='1' then
                  a5_instr <= '0';
               end if;
            end if;
         end if;
      end process;
      

   --------------------------------------------------------------------
   debug_ack_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               debug_ack <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if codefetcheff='1' then
                  if (debug_mode='1' and debugstep='0' and debugstep_ff='0') or
                     memdatai=UNKNOWN
                  then
                     debug_ack <= '1';
                  else
                     debug_ack <= '0';
                  end if;
               end if;
            end if;
         end if;
      end process;
      
   --------------------------------------------------------------------
   debug_ff_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               debugstep_ff <= '0';
               debugprog_ff <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- debugstep_ff write
               ----------------------------------
               if debugstep='1' and phase=4 then
                  debugstep_ff <= '1';
               elsif cycle=nrcycles and phase=3 and debug_ack='0' then
                  debugstep_ff <= '0';
               end if;
               ----------------------------------
               -- debugprog_ff write
               ----------------------------------
               if debugprog='1' and phase=4 then
                  debugprog_ff <= '1';
               elsif cycle=nrcycles and phase=3 and debug_ack='0' then
                  debugprog_ff <= '0';
               end if;

            end if;
         end if;
      end process;

   --------------------------------------------------------------------
   -- flush
   --------------------------------------------------------------------
   flush_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               flush <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if codefetche='1' then
                  if (  (debug_mode='1' and debugstep_ff='1') or
                        (debug_mode='0')
                     ) and flushff='1' 
                  then
                        flush <= '1';
                  end if;
               else
                  flush <= '0';
               end if;
            end if;
         end if;
      end process;
      
   --------------------------------------------------------------------
   -- data fetch or code fetch 
   --------------------------------------------------------------------
   fetch_write_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               fetch <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if codefetche='1' or datafetche='1' then
                  if (  (debug_mode='1' and debugstep_ff='1') or
                        (debug_mode='0')
                     ) and flushff='0' 
                  then
                        fetch <= '1';
                  end if;
               else
                  fetch <= '0';
               end if;
            end if;
         end if;
      end process;
   
   end RTL;
--*******************************************************************--