serial.vhd

51单片机内核vhdl实现 xilinx平台的

                     ) and 
                     (phase=4)
                  )
               then
               
                  -------------------------------
                  -- Mode 0
                  -------------------------------
                  if scon(7 downto 6)="00" then
                     t_shift_reg(8 downto 1) <= sbuf_t;
                     t_shift_reg(0)          <= '1';
                     t_shift_count           <= "1001";
                  end if;
               else 
                  if (
                        (t_shift_we='1') and 
                        (cycle=1 or
                         cycle=3 or
                         cycle=5 or
                         cycle=7
                        ) and 
                        (phase=1)
                     )
                  then
                  
                  -------------------------------
                  -- Mode 1
                  -------------------------------
                     if scon(7 downto 6)="01" then
                        t_shift_reg(10)         <= '1';             
                        t_shift_reg(9 downto 2) <= sbuf_t;     
                        t_shift_reg(1)          <= '0';          
                        t_shift_reg(0)          <= '1';          
                        t_shift_count           <= "1010";     
                     end if;
                  
                  -------------------------------
                  -- Mode 2, 3
                  -------------------------------
                     if (scon(7 downto 6)="10" or
                         scon(7 downto 6)="11")
                     then
                        t_shift_reg(10)         <= scon(3);
                        t_shift_reg(9 downto 2) <= sbuf_t;
                        t_shift_reg(1)          <= '0';
                        t_shift_reg(0)          <= '1';
                        t_shift_count           <= "1011";   
                     end if;  
                  
                  else
                  
                  ----------------------------------
                  -- Transmit register shift
                  ----------------------------------
                     if scon(7 downto 6)="00" then
                        if (
                              (cycle=2 or
                               cycle=4 or
                               cycle=6 or
                               cycle=8
                              ) and
                              (phase=4)
                           ) 
                        then  
                           t_shift_reg(9 downto 0) <= 
                              t_shift_reg(10 downto 1);
                        end if;
                     else
                        if t_shift_clk='1' then
                           t_shift_reg(9 downto 0) <= 
                              t_shift_reg(10 downto 1);
                        end if;
                     end if;
                  
                  ----------------------------------
                  -- Transmit data count
                  ----------------------------------
                     if t_shift_clk='1' then
                        if not (t_shift_count="0000") then
                           t_shift_count <= t_shift_count-'1';
                        end if;
                     end if;
                  
                  end if;
               
               ------------------------------------
               -- Transmit output
               ----------------------------------
                  if scon(7 downto 6)="00" then     -- mode 0 
                     if t_start='1' or r_start='1' then
                        if (receive = '1'or
                            t_start = '1')
                        then 
                           if (
                                 (
                                    (cycle=2 or
                                     cycle=4 or
                                     cycle=6 or
                                     cycle=8
                                    ) and 
                                    (phase=1 or
                                     phase=2)
                                 ) or
                                 (
                                    (cycle=1 or
                                     cycle=3 or
                                     cycle=5 or
                                     cycle=7
                                    ) and 
                                    (phase=3 or
                                     phase=4 or
                                     phase=5 or
                                     phase=6)
                                 )
                              )    
                           then  
                              if not (t_shift_count="0001") then
                                 txd <= '0';
                              end if;   
                           else
                              txd <= '1';   
                           end if;
                           rxdo <= t_shift_reg(1); 
                        else 
                           txd  <= '1';
                           rxdo <= '1';
                        end if;
                     end if;  
                  else   -- mode 1,2,3
                     if t_start_m='1' then
                        txd  <= t_shift_reg(0);
                     else
                        txd  <= '1';
                        rxdo <= '1';
                     end if;
                  end if;
               
               end if;
            
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   r_baud_ov_proc:
    --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
         
         -------------------------------------
         -- Synchronous reset
         -------------------------------------
            if rst='1' then
               r_baud_ov <= '0';
            else
            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
            
               if r_baud_count = "1111" then
                  r_baud_ov <= '1';
               else
                  r_baud_ov <= '0'; 
               end if;
            end if;
         end if;  
      end process;
   
   
   --------------------------------------------------------------------
   r_baud_clk_hand:
   --------------------------------------------------------------------
      r_baud_clk <=
         clk_ov12 when scon(7 downto 6)="00" else -- mode=0
         r_baud_ov;                               -- mode=1,2,3
   
   
   --------------------------------------------------------------------
   -- Falling edge detection on the external input rxdi
   -- rxd_fall is high active during single clk period
   --------------------------------------------------------------------
   rxd_fall_proc :
    --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
         
         -------------------------------------
         -- Synchronous reset
         -------------------------------------
            if rst='1' then
               rxd_fall <= '0';
               rxd_ff0  <= '0';
               rxd_ff   <= '0';
            else
            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
            ----------------------------------
            -- Falling edge detection
            ----------------------------------
               if rxd_ff0='0' and rxd_ff='1' then
                  rxd_fall <= '1';
               else
                  rxd_fall <= '0';
               end if;
            
            ----------------------------------
            -- t0 input flip-flop
            ----------------------------------
               rxd_ff0 <= rxdi;
               rxd_ff  <= rxd_ff0;
            
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- rxdi input pin falling edge detector
   --------------------------------------------------------------------
   rxd_vec_proc:
    --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
         
         -------------------------------------
         -- Synchronous reset
         -------------------------------------
            if rst='1' then
               rxd_vec  <= "111";
            else
            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
            -- RXD vector write
            ----------------------------------
               if b_clk='1' then
                  rxd_vec <= rxd_vec(1 downto 0) & rxd_ff0;
               end if;
            
            ----------------------------------
            -- rxd pin value
            ----------------------------------
               case scon(7 downto 6) is
                  when "00" =>     -- mode 0
                     if scon(5)='1' then
                        if clk_count(0)='1' then -- bit 0 - osc/2
                                                 -- bit 1 - osc/4
                           rxd_val <= rxd_ff0;
                        end if;
                     else
                        if clk_count(2)='1' then
                           rxd_val <= rxd_ff0;
                        end if;
                     end if;
               
                  when others =>   -- mode 1,2,3
                     if (rxd_vec="001" or
                         rxd_vec="010" or
                         rxd_vec="100" or
                         rxd_vec="000")
                     then
                        rxd_val <= '0';
                     else
                        rxd_val <= '1';
                     end if;
               
               end case;
            
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Rising edge detection on the r_start 
   -- r_start_rise is high active during single clk period
   --------------------------------------------------------------------
   r_start_rise_proc :
    --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
         
         -------------------------------------
         -- Synchronous reset
         -------------------------------------
            if rst='1' then
               r_start_rise <= '0';
               r_start_ff   <= '0';
            else
            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
            -- Falling edge detection
            ----------------------------------
               if r_start='1' and r_start_ff='0' then
                  r_start_rise <= '1';
               else
                  r_start_rise <= '0';
               end if;