serial.vhd

51单片机内核vhdl实现 xilinx平台的

               sbuf_t  <= SBUF_RV;
            else
            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
            -- Special function register write
            ----------------------------------
               if (sfrwe='1' and sfraddr=SBUF_ID) then   
                  sbuf_t <= sfrdatai;
               
               
               end if;
            
            end if;
         end if;
      end process;
   
   --------------------------------------------------------------------
   t_shift_we_write_proc:
    --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
         
         -------------------------------------
         -- Synchronous reset
         -------------------------------------
            if rst='1' then
               t_shift_we  <= '0';
            else
            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
            -- Special function register write
            ----------------------------------
               if (sfrwe='1' and sfraddr=SBUF_ID) then  
                  t_shift_we <= '1';
               elsif (
                        (t_shift_we='1') and
                        (cycle=2 or
                         cycle=4 or
                         cycle=6 or
                         cycle=8
                        ) and 
                        (phase=4)
                     )
               then
                  t_shift_we <= '0';
               end if;
            
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   clk_count_proc:
    --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
         
         -------------------------------------
         -- Synchronous reset
         -------------------------------------
            if rst='1' then
               clk_count <= "0000";
               clk_ov2   <= '0';
               clk_ov12  <= '0';
            else
            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
            -- clk counter
            ----------------------------------
               if clk_count="1011" then
                  clk_count <= "0000";
               else
                  clk_count <= clk_count + '1';
               end if;
            
            ----------------------------------
            -- clk divide by 2
            ----------------------------------
               if clk_count(0)='1' then
                  clk_ov2 <= '1';
               else
                  clk_ov2 <= '0';
               end if;
            
            ----------------------------------
            -- clk divide by 12
            ----------------------------------
               if clk_count="1011" then
                  clk_ov12 <= '1';
               else
                  clk_ov12 <= '0';
               end if;
            
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   baud_clk_sel:  
    --------------------------------------------------------------------
      process (scon, smod, baud_r_clk, baud_r2_clk)
      begin
         case scon(7 downto 6) is
         -------------------------------------
         -- Modes 1, 2 or 3
         -------------------------------------
            when "01" | "11" | "10" =>
               if smod='1' then
                  b_clk <= baud_r_clk;
               else 
                  b_clk <= baud_r2_clk;
               end if;
         -------------------------------------
         -- Mode 0
         -------------------------------------
            when others =>
               b_clk <= '0';
         
         end case;
      end process;
   
   
   --------------------------------------------------------------------
   baud_r_clk_sel:
   --------------------------------------------------------------------
      baud_r_clk <= 
         t1ov_rise when (scon(7 downto 6)="01" or
                         scon(7 downto 6)="11") else
         clk_ov2; 
   
   
   --------------------------------------------------------------------
   baud_div_proc:
    --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
         
         -------------------------------------
         -- Synchronous reset
         -------------------------------------
            if rst='1' then
               baud_r_count <= '0';
               baud_r2_clk  <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
            -- baud_r_clk overflow count
            ----------------------------------
               if baud_r_clk='1' then
                  baud_r_count <= not(baud_r_count);
               end if;
            
            ----------------------------------
            -- Overflow divide by 2
            ----------------------------------
               if (baud_r_clk='1' and baud_r_count='1') then
                  baud_r2_clk <= '1';
               else
                  baud_r2_clk <= '0';
               end if;
            
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   t_baud_clk_hand:
   --------------------------------------------------------------------
      t_baud_clk <=
         '1' when (
                     (cycle=2 or
                      cycle=4 or
                      cycle=6 or
                      cycle=8
                     ) and 
                     (phase=4) and
                     (scon(7 downto 6)="00")
                  ) else -- mode=0
         t_baud_ov;      -- mode=1,2,3
   
   
   
   --------------------------------------------------------------------
   t_shift_clk_hand:
   --------------------------------------------------------------------
      t_shift_clk <=
         t_baud_clk when (t_start='1' and
                          scon(7 downto 6)="00")  else
         t_baud_clk when (t_start_m='1' and
                          not (scon(7 downto 6)="00")) else
         '0';
   
   
   --------------------------------------------------------------------
   transmit_proc:
    --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
         
         -------------------------------------
         -- Synchronous reset
         -------------------------------------
            if rst='1' then
               t_start         <= '0';
               t_start_m       <= '0';
               t_baud_count    <= "0000";
               t_baud_ov       <= '0';
               t_shift_reg     <= "11111111111";
               t_shift_count   <= "0000";
               txd             <= '1';
               rxdo            <= '1';
            else
            
            -------------------------------------
            -- Synchronous write
            -------------------------------------
            -- Transmit clk divide by 16
            ----------------------------------
               if b_clk='1' then
                  t_baud_count <= t_baud_count + '1';
               end if;
            
               if (b_clk='1' and t_baud_count="1110") then  
                  t_baud_ov <= '1';
               else
                  t_baud_ov <= '0';
               end if;
            
            ----------------------------------
            -- Transmit shift counter
            ----------------------------------
            -- mode 1,2,3
            ----------------------------------
               if (t_shift_count="0000" and 
                   not (
                          (t_shift_we='1') and
                          (cycle=2 or
                           cycle=4 or
                           cycle=6 or 
                           cycle=8
                          ) and 
                          (phase=4)
                       )
                  )
               then 
                  t_start <= '0';
               elsif (
                        (t_shift_we='1') and
                        (cycle=2 or
                         cycle=4 or
                         cycle=6 or
                         cycle=8
                        ) and 
                        (phase=4)
                     )
               then
                  t_start <= '1';
               end if; 
            
            ----------------------------------
            -- mode 0
            ---------------------------------- 
               if (t_shift_count="0000" and 
                   not (
                          (t_shift_we='1') and 
                          (cycle=1 or
                           cycle=3 or
                           cycle=5 or
                           cycle=7
                          ) and 
                       phase=1)
                  )
               then 
                  t_start_m <= '0';
               elsif (
                        (t_shift_we='1') and
                        (cycle=1 or
                         cycle=3 or
                         cycle=5 or
                         cycle=7
                        ) and 
                        (phase=1)
                     )
               then
                  t_start_m <= '1';
               end if;
            
            ----------------------------------
            -- Transmit registers load
            ----------------------------------
               if (
                     (t_shift_we='1') and
                     (cycle=2 or
                      cycle=4 or
                      cycle=6 or
                      cycle=8