isr.vhd

51单片机内核vhdl实现 xilinx平台的

            -- Synchronous write
            -------------------------------------
               if phase=6 then
                  int_req <= not debugmode and 
                        (ie(7)) and 
                        (
                           (l1 and not is_reg(1) ) or
                           (l0 and not is_reg(0) and not is_reg(1))
                        
                        );
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- interrupt request
   --------------------------------------------------------------------
   intreq_write_proc:
   --------------------------------------------------------------------
      process(clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               intreq <= '0';
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if phase=3 then
                  if not(
                           (instr=RETI) or
                           (
                              (instr=INC_ADDR     or instr=DEC_ADDR      or
                               instr=ANL_ADDR_A   or instr=ANL_ADDR_N    or
                               instr=ORL_ADDR_A   or instr=ORL_ADDR_N    or
                               instr=XRL_ADDR_A   or instr=XRL_ADDR_N    or
                               instr=MOV_ADDR_A   or instr=MOV_ADDR_R0   or
                               instr=MOV_ADDR_R1  or instr=MOV_ADDR_R2   or
                               instr=MOV_ADDR_R3  or instr=MOV_ADDR_R4   or
                               instr=MOV_ADDR_R5  or instr=MOV_ADDR_R6   or
                               instr=MOV_ADDR_R7  or instr=MOV_ADDR_ADDR or
                               instr=MOV_ADDR_IR0 or instr=MOV_ADDR_IR1  or
                               instr=MOV_ADDR_N   or instr=POP           or
                               instr=CLR_BIT      or instr=SETB_BIT      or
                               instr=CPL_BIT      or instr=MOV_BIT_C     or
                               instr=JBC_BIT      or instr=DJNZ_ADDR     
                              ) and
                              (sfraddr=IE_ID or
                               sfraddr=IP_ID
                              )
                           )
                        ) 
                  then
                     intreq <=int_req;
                  else
                     intreq <='0';
                  end if;
               end if;
            end if;
         end if;
      end process; 
   
   
   --------------------------------------------------------------------
   -- interrupt vector
   --------------------------------------------------------------------
   int_vect_write_comb_proc:
   --------------------------------------------------------------------
      process(intreql0, intreql1, l1)
      begin
         if l1 = '1' then
            intreq_vect <= intreql1;
         else
            intreq_vect <= intreql0;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- combinational vector locations
   --------------------------------------------------------------------
   vect_write_comb_proc:
   --------------------------------------------------------------------
      process(intreq_vect)
      begin
         if intreq_vect(0)='1' then
            vect <= VECT_EXT0;
         else
            if intreq_vect(1)='1' then
               vect <= VECT_TF0;
            else
               if intreq_vect(2)='1' then
                  vect <= VECT_EXT1;
               else
                  if intreq_vect(3)='1' then
                     vect <= VECT_TF1;
                  else
                     --if intreq_vect(4)='1' then
                     vect <= VECT_RITI;
                  end if;
               end if;
            end if;
         end if;
      
      end process;
   
   
   --------------------------------------------------------------------
   -- vector locations
   -- registered section
   --------------------------------------------------------------------
   int_vect_write_sync_proc:
   --------------------------------------------------------------------
      process (clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               int_vect <= "000";
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               if phase=6 then
                  int_vect <= vect;
               end if;
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- In Service Register
   -- Combinational section
   --------------------------------------------------------------------
   is_reg_comb_proc:
   --------------------------------------------------------------------
      process(is_reg, l1, intret)
      begin
         if intret='1' then
            if is_reg(1)='1' then
               is_nxt <= "0" & is_reg(0);
            else
               is_nxt <= "00";
            end if;
         else
            if l1='1' then 
               is_nxt <= "1" & is_reg(0);
            else 
               is_nxt <= "01";
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- In Service Register
   -- Registered section
   --------------------------------------------------------------------
   is_reg_sync_proc:
   --------------------------------------------------------------------
      process(clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               is_reg <= "00";
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- In Service Register write
               ----------------------------------
               if (intack='1' or intret='1') then
                  is_reg <= is_nxt;
               end if;
            end if;
         end if;
      end process; 
   
   
   --------------------------------------------------------------------
   -- Interrupt acknowledge output flags
   --------------------------------------------------------------------
   ackbits_sync_proc :
   --------------------------------------------------------------------
      process(clk)
      begin
         if clk'event and clk='1' then
            -------------------------------------
            -- Synchronous reset
            -------------------------------------
            if rst='1' then
               int0ack <= '0';   -- External interrupt 0 acknowledge
               int1ack <= '0';   -- External interrupt 1 acknowledge
               t0ack <= '0';     -- Timer 0 interrupt acknowledge
               t1ack <= '0';     -- Timer 1 interrupt acknowledge
            else
            -------------------------------------
            -- Synchronous write
            -------------------------------------
               -- External interrupt 0 acknowledge
               ----------------------------------
               if (intack = '1') and (int_vect = VECT_EXT0) then
                  int0ack <= '1';
               else
                  int0ack <= '0';
               end if;
            
               ----------------------------------
               -- External interrupt 1 acknowledge
               ----------------------------------
               if (intack = '1') and (int_vect = VECT_EXT1) then
                  int1ack <= '1';
               else
                  int1ack <= '0';
               end if;
            
               ----------------------------------
               -- Timer 0 interrupt acknowledge
               ----------------------------------
               if (intack = '1') and (int_vect = VECT_TF0) then
                  t0ack <= '1';
               else
                  t0ack <= '0';
               end if;
            
               ----------------------------------
               -- Timer 1 interrupt acknowledge
               ----------------------------------
               if (intack = '1') and (int_vect = VECT_TF1) then
                  t1ack <= '1';
               else
                  t1ack <= '0';
               end if;
            
            end if;
         end if;
      end process;
   
   
   --------------------------------------------------------------------
   -- Special Function registers read
   --------------------------------------------------------------------
   sfr_read :
   --------------------------------------------------------------------
      sfrdataisr <=
         ie   when sfraddr=IE_ID else
         ip   when sfraddr=IP_ID else
         "--------";
   
   
   end RTL;
--*******************************************************************--