📄 tb.vhd
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--*******************************************************************--
-- Copyright (c) 1999-2001 Evatronix SA --
--*******************************************************************--
-- Please review the terms of the license agreement before using --
-- this file. If you are not an authorized user, please destroy this --
-- source code file and notify Evatronix SA immediately that you --
-- inadvertently received an unauthorized copy. --
--*******************************************************************--
-----------------------------------------------------------------------
-- Project name : C8051
-- Project description : C8051 Microcontroller Unit
--
-- File name : TB.VHD
-- File contents : Entity TB_C8051
-- Architecture STRUCTURAL of TB_C8051
-- Configuration TYPICAL_C8051_EXTRAM_EXTROM
-- of TB_C8051
-- Purpose : Top-level structure of TB_C8051
--
-- Destination library : C8051_LIB
-- Dependencies : IEEE.STD_LOGIC_1164
-- STD.TEXTIO
--
-- Design Engineer : M.B.
-- Quality Engineer : M.B.
-- Version : 3.01
-- Last modification : 2001-10-01
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library C8051_LIB;
entity TB_C8051 is
generic (
TESTNAME : STRING := "default";
TESTPATH : STRING := "tests/"
);
end TB_C8051;
--*******************************************************************--
architecture STRUCTURAL of TB_C8051 is
-----------------------------------------------------------------
-- Test Bench file names
-----------------------------------------------------------------
constant INTROMFILE : STRING := "introm.hex";
constant EXTROMFILE : STRING := "extrom.hex";
constant SIMCOMPFILE : STRING := "simcomp.txt";
constant SIMDIFFFILE : STRING := "simdiff.txt";
constant ACSCOMPFILE : STRING := "acscomp.txt";
constant ACSDIFFFILE : STRING := "acsdiff.txt";
constant STIMFILE : STRING := "stim.txt";
-----------------------------------------------------------------
-- Test Bench environment parameters
-----------------------------------------------------------------
constant INTRAMSIZE : INTEGER := 8; -- Internal RAM size index
constant INTROMSIZE : INTEGER := 14; -- Internal ROM size index
constant EXTRAMSIZE : INTEGER := 16; -- External RAM size index
constant EXTROMSIZE : INTEGER := 16; -- External ROM size index
constant SYNCSTART : TIME := 4000 ns; --Synchronize start
constant SYNCSTOP : TIME := 5540 ns; --Synchronize stop
constant CLOCKPERIOD : TIME := 20 ns; -- Clock pulse period
constant CLOCKDUTY : INTEGER := 50; -- Duty cycle (0-100%)
constant SIMCOMPDUTY : INTEGER := 90; -- Recognize point (0-100%)
constant SIMCOMPMODE : INTEGER := 2; -- SIM Comparator mode
constant ACSCOMPMODE : INTEGER := 2; -- ACS Comparator mode
-- SIM and ACS Comparator modes description:
-- 0 - no occurrence
-- 1 - the COMPFILE writer
-- 2 - vectors comparator
-- Synchronization sample settings
-- Fclk CLOCKPERIOD SYNCSTOP
-- 50 MHz 20 ns 5540 ns
-- 25 MHz 40 ns 6080 ns
-----------------------------------------------------------------
component CHIP_C8051
-----------------------------------------------------------------
generic (
RAMSIZE : INTEGER := 8; -- RAM size index
ROMSIZE : INTEGER := 14; -- ROM size index
ROMFILE : STRING := "INTROM.HEX"; -- ROM init file
FILEPATH : STRING := "TB/" -- Path to the ROM init file
);
port (
-- Input ports
reset : in STD_LOGIC; -- Hardware reset input
xtal1 : in STD_LOGIC; -- Oscilator input
ea : in STD_LOGIC; -- External Access input
-- Bidirectional ports
p0 : inout STD_LOGIC_VECTOR(7 downto 0);
p1 : inout STD_LOGIC_VECTOR(7 downto 0);
p2 : inout STD_LOGIC_VECTOR(7 downto 0);
p3 : inout STD_LOGIC_VECTOR(7 downto 0);
-- Output ports
psen : out STD_LOGIC; -- Program Store Enable
ale : out STD_LOGIC; -- Address Latch Enable
xtal2 : out STD_LOGIC -- Oscilator output
);
end component;
-----------------------------------------------------------------
component EXTERNAL_CLOCK_GENERATOR
-----------------------------------------------------------------
generic (
PERIOD : TIME := 100 ns; -- Clock pulse period
DUTY : INTEGER := 50; -- Duty cycle (0-100%)
SYNCSTART : TIME := 1000 ns;
SYNCSTOP : TIME := 2500 ns
);
port (
reset : in STD_LOGIC;
ale : in STD_LOGIC;
clk : out STD_LOGIC
);
end component;
-----------------------------------------------------------------
component EXTERNAL_LATCH_REGISTER
-----------------------------------------------------------------
generic (
DATAWIDTH : INTEGER := 8
);
port (
strobe : in STD_LOGIC;
databusi : in STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0);
databuso : out STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0)
);
end component;
-----------------------------------------------------------------
component EXTERNAL_SHIFT_REGISTER
-----------------------------------------------------------------
generic (
DATAWIDTH : INTEGER := 8
);
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
we : in STD_LOGIC;
oe : in STD_LOGIC;
biti : in STD_LOGIC;
bito : out STD_LOGIC
);
end component;
-----------------------------------------------------------------
component EXTERNAL_DATA_MEMORY
-----------------------------------------------------------------
generic (
DATAWIDTH : INTEGER := 8;
ADDRWIDTH : INTEGER := 16
);
port (
addrbus : in STD_LOGIC_VECTOR (ADDRWIDTH-1 downto 0);
rd : in STD_LOGIC;
wr : in STD_LOGIC;
databusi : in STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0);
databuso : out STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0)
);
end component;
-----------------------------------------------------------------
component EXTERNAL_PROGRAM_MEMORY
-----------------------------------------------------------------
generic (
DATAWIDTH : INTEGER := 8;
ADDRWIDTH : INTEGER := 16;
ROMFILE : STRING := "extrom.hex"; -- Memory init file
FILEPATH : STRING := "tests/default/" -- Path to the init file
);
port (
addrbus : in STD_LOGIC_VECTOR (ADDRWIDTH-1 downto 0);
rd : in STD_LOGIC;
databus : out STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0)
);
end component;
-----------------------------------------------------------------
component EXTERNAL_STIMULATOR
-----------------------------------------------------------------
generic (
STIMFILE : STRING := "stim.txt"; -- Stimulus file
FILEPATH : STRING := "tests/default"-- Path to the stim file
);
port (
p0 : out STD_LOGIC_VECTOR (7 DOWNTO 0);
p1 : out STD_LOGIC_VECTOR (7 DOWNTO 0);
p2 : out STD_LOGIC_VECTOR (7 DOWNTO 0);
p3 : out STD_LOGIC_VECTOR (7 DOWNTO 0);
rst : out STD_LOGIC;
ea : out STD_LOGIC
);
end component;
-----------------------------------------------------------------
component EXTERNAL_COMPARATOR
-----------------------------------------------------------------
generic (
MODE : INTEGER := 2; -- Comparator mode
-- 0 - no occurrence
-- 1 - the COMPFILE writer
-- 2 - vectors comparator
DUTY : INTEGER := 90; -- recognize point (0-100%)
TESTNAME : STRING := "default";
TESTPATH : STRING := "tests/";
COMPFILE : STRING := "simcomp.txt"; -- Compare file
DIFFFILE : STRING := "simdiff.txt" -- Differ. file
);
port (
p0 : in STD_LOGIC_VECTOR (7 DOWNTO 0);
p1 : in STD_LOGIC_VECTOR (7 DOWNTO 0);
p2 : in STD_LOGIC_VECTOR (7 DOWNTO 0);
p3 : in STD_LOGIC_VECTOR (7 DOWNTO 0);
rst : in STD_LOGIC;
ale : in STD_LOGIC;
psen : in STD_LOGIC;
ea : in STD_LOGIC;
clk : in STD_LOGIC
);
end component;
-----------------------------------------------------------------
component EXTERNAL_ACCESS_COMPARATOR
-----------------------------------------------------------------
generic (
MODE : INTEGER := 2; -- Comparator mode
-- 0 - no occurrence
-- 1 - the COMPFILE writer
-- 2 - vectors comparator
DATAWIDTH : INTEGER := 8;
ADDRWIDTH : INTEGER := 16;
TESTNAME : STRING := "default";
TESTPATH : STRING := "tests/";
COMPFILE : STRING := "asccomp.txt"; -- Compare file
DIFFFILE : STRING := "ascdiff.txt" -- Differ. file
);
port (
rst : in STD_LOGIC;
addrbus : in STD_LOGIC_VECTOR (ADDRWIDTH-1 downto 0);
databus : in STD_LOGIC_VECTOR (DATAWIDTH-1 downto 0);
wr : in STD_LOGIC
);
end component;
-----------------------------------------------------------------
component D80530HM_tb
-----------------------------------------------------------------
port(
p0 : in STD_LOGIC_VECTOR(7 downto 0);
ale : in STD_LOGIC
);
end component;
-----------------------------------------------------------------
-- Test Bench interconnection signals
-----------------------------------------------------------------
signal reset : STD_LOGIC; -- Global reset input
signal xtal1 : STD_LOGIC; -- Oscilator input
signal ea : STD_LOGIC; -- External access enable
signal p0 : STD_LOGIC_VECTOR(7 downto 0);
signal p1 : STD_LOGIC_VECTOR(7 downto 0);
signal p2 : STD_LOGIC_VECTOR(7 downto 0);
signal p3 : STD_LOGIC_VECTOR(7 downto 0);
signal psen : STD_LOGIC; -- Program store read enable
signal ale : STD_LOGIC; -- Address Latch Enable
signal xtal2 : STD_LOGIC; -- Oscilator output
signal addrbus : STD_LOGIC_VECTOR(15 downto 0);
signal owt : STD_LOGIC; -- Oscillator Watchdog Timer
-----------------------------------------------------------------
-- Indirect drivers for Shift Register 0
-----------------------------------------------------------------
signal shift0_clk : STD_LOGIC;
signal shift0_we : STD_LOGIC;
signal shift0_oe : STD_LOGIC;
signal shift0_biti : STD_LOGIC;
signal shift0_bito : STD_LOGIC;
-----------------------------------------------------------------
-- Indirect drivers for Shift Register 1
-----------------------------------------------------------------
signal shift1_clk : STD_LOGIC;
signal shift1_we : STD_LOGIC;
signal shift1_oe : STD_LOGIC;
signal shift1_biti : STD_LOGIC;
signal shift1_bito : STD_LOGIC;
-----------------------------------------------------------------
-- Power and ground signals
-----------------------------------------------------------------
signal high : STD_LOGIC;
signal low : STD_LOGIC;
-----------------------------------------------------------------
-- Indirect drivers for Data Memory
-----------------------------------------------------------------
signal ram_rd : STD_LOGIC; -- Data Memory write
signal ram_wr : STD_LOGIC; -- Data Memory read
-----------------------------------------------------------------
-- Indirect drivers for ACS Comparator
-----------------------------------------------------------------
signal acscomp_wr : STD_LOGIC;
-- OCI signals
signal debugreq : STD_LOGIC; -- debug mode request
signal debugstep : STD_LOGIC; -- debug mode single-step
signal debugprog : STD_LOGIC; -- debugger program select
signal debugack : STD_LOGIC; -- debugger acknowledge signal
signal flush : STD_LOGIC; -- branch instruction fetch
signal fetch : STD_LOGIC; -- no-branch instruction fetch
signal acc : STD_LOGIC_VECTOR(7 downto 0);
begin
debugreq <= '0';
debugstep <= '0';
debugprog <= '0';
--------------------------------------------------------------------
-- Power and ground signals
--------------------------------------------------------------------
vcc : high <= '1';
gnd : low <= '0';
--------------------------------------------------------------------
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