📄 tb_mc8051_siu_sim.vhd
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--------------------------------------------------------------------------------- ---- X X XXXXXX XXXXXX XXXXXX XXXXXX X ---- XX XX X X X X X X X XX ---- X X X X X X X X X X X X ---- X X X X X X X X X X X X ---- X X X X XXXXXX X X XXXXXX X ---- X X X X X X X X X ---- X X X X X X X X X ---- X X X X X X X X X X ---- X X XXXXXX XXXXXX XXXXXX XXXXXX X ---- ---- ---- O R E G A N O S Y S T E M S ---- ---- Design & Consulting ---- ----------------------------------------------------------------------------------- ---- Web: http://www.oregano.at/ ---- ---- Contact: mc8051@oregano.at ---- ----------------------------------------------------------------------------------- ---- MC8051 - VHDL 8051 Microcontroller IP Core ---- Copyright (C) 2001 OREGANO SYSTEMS ---- ---- This library is free software; you can redistribute it and/or ---- modify it under the terms of the GNU Lesser General Public ---- License as published by the Free Software Foundation; either ---- version 2.1 of the License, or (at your option) any later version. ---- ---- This library is distributed in the hope that it will be useful, ---- but WITHOUT ANY WARRANTY; without even the implied warranty of ---- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ---- Lesser General Public License for more details. ---- ---- Full details of the license can be found in the file LGPL.TXT. ---- ---- You should have received a copy of the GNU Lesser General Public ---- License along with this library; if not, write to the Free Software ---- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ---- --------------------------------------------------------------------------------------- Author: Roland H鰈ler---- Filename: tb_mc8051_siu_sim.vhd---- Date of Creation: Mon Aug 9 12:14:48 1999---- Version: $Revision: 1.5 $---- Date of Latest Version: $Date: 2002/01/07 12:16:57 $------ Description: Module level testbench for the serial interface -- unit.---------------------------------------------------------------------------------------architecture sim of tb_mc8051_siu is signal clk : std_logic; --< system clock signal reset : std_logic; --< system reset signal s_tf : std_logic; --< timer1 overflow flag signal s_trans : std_logic; --< 1 activates transm. signal s_rxd : std_logic; --< serial data input signal s_scon : std_logic_vector(5 downto 0); --< from SFR register --< bits 7 to 3 signal s_sbuf : std_logic_vector(7 downto 0); --< data for transm. signal s_smod : std_logic; --< low(0)/high baudrate signal s_sbuf_out : std_logic_vector(7 downto 0); --< received data signal s_scon_out : std_logic_vector(2 downto 0); --< to SFR register --< bits 0 to 2 signal s_rxd_out : std_logic; --< mode0 data output signal s_txd_out : std_logic; --< serial data output signal clk_p : std_logic; --< system clock signal s_tf_p : std_logic; --< timer1 overflow flag signal s_trans_p : std_logic; --< 1 activates transm. signal s_rxd_p : std_logic; --< serial data input signal s_rxd0_p : std_logic; --< serial data input signal s_rxd1_p : std_logic; --< serial data input signal s_rxd2_p : std_logic; --< serial data input signal s_rxd3_p : std_logic; --< serial data input signal s_scon_p : std_logic_vector(5 downto 0); --< from SFR register --< bits 7 to 3 signal s_sbuf_p : std_logic_vector(7 downto 0); --< data for transm. signal s_smod_p : std_logic; --< low(0)/high baudrate signal s_sbuf_out_p : std_logic_vector(7 downto 0); --< received data signal s_scon_out_p : std_logic_vector(2 downto 0); --< to SFR register --< bits 0 to 2 signal s_rxdwr : std_logic; --< rxd direction signal signal s_rxdwr_p : std_logic; --< rxd direction signal signal s_rxd_out_p : std_logic; --< mode0 data output signal s_txd_out_p : std_logic; --< serial data output signal s_serialdata : std_logic; begin s_serialdata <= s_txd_out when s_scon(4 downto 3) /= "00" else s_rxd_out; i_mc8051_siu_active : mc8051_siu port map (clk => clk, reset => reset, tf_i => s_tf, trans_i => s_trans, rxd_i => s_rxd, scon_i => s_scon, sbuf_i => s_sbuf, smod_i => s_smod, sbuf_o => s_sbuf_out, scon_o => s_scon_out, rxdwr_o => s_rxdwr, rxd_o => s_rxd_out, txd_o => s_txd_out); i_mc8051_siu_passive : mc8051_siu port map (clk => clk_p, reset => reset, tf_i => s_tf_p, trans_i => s_trans_p, rxd_i => s_serialdata, scon_i => s_scon_p, sbuf_i => s_sbuf_p, smod_i => s_smod_p, sbuf_o => s_sbuf_out_p, scon_o => s_scon_out_p, rxdwr_o => s_rxdwr_p, rxd_o => s_rxd_out_p, txd_o => s_txd_out_p);--------------------------------------------------------------------------------- Perform simple selfchecking test for the four operating modes.------------------------------------------------------------------------------- p_run : process begin ------------------------------------------------------------------------- -- set start values and perform reset ------------------------------------------------------------------------- s_rxd <= '0'; s_smod <= '0'; s_trans <= '0'; s_sbuf <= conv_std_logic_vector(0, 8); s_scon <= conv_std_logic_vector(0, 6); s_smod_p <= '0'; s_trans_p <= '0'; s_sbuf_p <= conv_std_logic_vector(0, 8); s_scon_p <= conv_std_logic_vector(0, 6); reset <= '1'; wait for one_period + one_period/2 + 5 ns; reset <= '0'; wait for one_period * 4; ------------------------------------------------------------------------- -- Testing MODE 0 ------------------------------------------------------------------------- s_scon <= conv_std_logic_vector(0, 6); -- 000000 s_sbuf <= conv_std_logic_vector(170, 8); -- 10101010 s_scon_p <= conv_std_logic_vector(2, 6); -- 000010 s_sbuf_p <= conv_std_logic_vector(170, 8); -- 10101010 s_trans <= '1'; -- start transmission wait for one_period * 1; s_trans <= '0'; wait until s_scon_out_p(0) = '1'; s_scon_p <= conv_std_logic_vector(0, 6); -- 000000 assert s_sbuf_out_p = "10101010" report "FALSE DATA RECEIVED IN MODE 0! DATA SENT: AAh" severity failure; wait for one_period * 600; s_scon <= conv_std_logic_vector(0, 6); -- 000000 s_sbuf <= conv_std_logic_vector(85, 8); -- 01010101 s_scon_p <= conv_std_logic_vector(2, 6); -- 000010 s_sbuf_p <= conv_std_logic_vector(16#55#, 8); -- 01010101 s_trans <= '1'; -- start transmission wait for one_period * 1; s_trans <= '0'; wait until s_scon_out_p(0) = '1'; s_scon_p <= conv_std_logic_vector(0, 6); -- 000000 assert s_sbuf_out_p = "01010101" report "FALSE DATA RECEIVED IN MODE 0! DATA SENT: 55h" severity failure; wait for one_period * 600; ------------------------------------------------------------------------- -- Testing MODE 1 ------------------------------------------------------------------------- s_smod <= '1'; s_scon <= conv_std_logic_vector(48, 6); -- 110000 MODE 1 + RI=1 s_sbuf <= conv_std_logic_vector(170, 8); -- 10101010 s_smod_p <= '1'; s_scon_p <= conv_std_logic_vector(18, 6); -- 010010 MODE 1 + RI=0 s_sbuf_p <= conv_std_logic_vector(170, 8); -- 10101010 s_trans <= '1'; -- start transmission wait for one_period * 1; s_trans <= '0'; wait until s_scon_out_p(0) = '1'; assert s_sbuf_out_p = "10101010" report "FALSE DATA RECEIVED IN MODE 1! DATA SENT: AAh" severity failure; wait for one_period * 600; s_sbuf <= conv_std_logic_vector(85, 8); -- 01010101 s_trans <= '1'; -- start transmission wait for one_period * 1; s_trans <= '0'; wait until s_scon_out_p(0) = '1'; assert s_sbuf_out_p = "01010101" report "FALSE DATA RECEIVED IN MODE 1! DATA SENT: 55h" severity failure; wait for one_period * 600; ------------------------------------------------------------------------- -- Testing MODE 2 ------------------------------------------------------------------------- s_smod <= '1'; s_scon <= conv_std_logic_vector(8, 6); -- 001000 MODE 2 s_sbuf <= conv_std_logic_vector(171, 8); -- 10101011 s_smod_p <= '1'; s_scon_p <= conv_std_logic_vector(10, 6); -- 001010 MODE 2 + REN=1 s_sbuf_p <= conv_std_logic_vector(171, 8); -- 10101011 s_trans <= '1'; -- start transmission wait for one_period * 1; s_trans <= '0'; wait until s_scon_out_p(0) = '1'; assert s_sbuf_out_p = "10101011" report "FALSE DATA RECEIVED IN MODE 2! DATA SENT: ABh" severity failure; wait for one_period * 400; s_sbuf <= conv_std_logic_vector(86, 8); -- 01010110 s_trans <= '1'; -- start transmission wait for one_period * 1; s_trans <= '0'; wait until s_scon_out_p(0) = '1'; assert s_sbuf_out_p = "01010110" report "FALSE DATA RECEIVED IN MODE 2! DATA SENT: 56h" severity failure; wait for one_period * 400; ------------------------------------------------------------------------- -- Testing MODE 3 ------------------------------------------------------------------------- s_scon <= conv_std_logic_vector(16#78#, 6); -- 111000 MODE 3 + RI=1 s_sbuf <= conv_std_logic_vector(16#BE#, 8); -- 10111110 s_scon_p <= conv_std_logic_vector(16#1A#, 6); -- 011010 MODE 3 + REN=1 s_trans <= '1'; -- start transmission wait for one_period * 1; s_trans <= '0'; wait until s_scon_out_p(0) = '1'; assert s_sbuf_out_p = "10111110" report "FALSE DATA RECEIVED IN MODE 3! DATA SENT: BEh" severity failure; wait for one_period * 4000; s_sbuf <= conv_std_logic_vector(16#55#, 8); -- 01010101 s_smod <= '0'; s_smod_p <= '0'; s_trans <= '1'; -- start transmission wait for one_period * 1; s_trans <= '0'; wait until s_scon_out_p(0) = '1'; assert s_sbuf_out_p = "01010101" report "FALSE DATA RECEIVED IN MODE 3! DATA SENT: 55h" severity failure; wait for one_period * 4000; s_smod <= '1'; s_scon <= conv_std_logic_vector(26, 6); -- 011010 start reception wait for one_period * 7560; ------------------------------------------------------------------------- -- END of test ------------------------------------------------------------------------- wait for one_period * 10; assert false report "SIMULATION ENDED WITHOUT ERROR!!" severity failure; end process p_run;---------------------------------------------------------------------------------------------------------------------------------------------------------------- System clock definition------------------------------------------------------------------------------- clk_p <= clk after 37 ns; p_clock : process variable v_loop1 : integer; begin clk <= '0'; wait for one_period / 2; while true loop clk <= not clk; wait for one_period / 2; end loop; end process p_clock;---------------------------------------------------------------------------------------------------------------------------------------------------------------- Generate timer1 overflow flag------------------------------------------------------------------------------- s_tf_p <= s_tf after 200 ns; p_tf : process variable v_loop1 : integer; begin s_tf <= '0'; wait for one_period + one_period / 2 + 5 ns; if s_scon(4 downto 3) = conv_std_logic_vector(2, 2) then -- Mode 1 while true loop s_tf <= not s_tf; wait for one_period * 20; end loop; else s_tf <= '0'; end if; end process p_tf;-------------------------------------------------------------------------------end sim;⌨️ 快捷键说明
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