stm32f10x_tim.txt

STM32F103ZET6+UCOSII+UCGUI源码

000000  b570              PUSH     {r4-r6,lr}
;;;586    {
000002  460d              MOV      r5,r1
000004  4604              MOV      r4,r0
;;;587      /* Check the parameters */
;;;588      assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;589      assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
;;;590      assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
;;;591      assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
;;;592      assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
;;;593      assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
;;;594      
;;;595      if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
000006  8808              LDRH     r0,[r1,#0]
;;;596      {
;;;597        /* TI1 Configuration */
;;;598        TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
000008  8849              LDRH     r1,[r1,#2]
00000a  88aa              LDRH     r2,[r5,#4]
00000c  892b              LDRH     r3,[r5,#8]
00000e  b940              CBNZ     r0,|L38.34|
000010  4620              MOV      r0,r4
000012  f7fffffe          BL       TI1_Config
;;;599                   TIM_ICInitStruct->TIM_ICSelection,
;;;600                   TIM_ICInitStruct->TIM_ICFilter);
;;;601    
;;;602        /* Set the Input Capture Prescaler value */
;;;603        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000016  88e9              LDRH     r1,[r5,#6]
000018  4620              MOV      r0,r4
00001a  e8bd4070          POP      {r4-r6,lr}
00001e  f7ffbffe          B.W      TIM_SetIC1Prescaler
                  |L38.34|
;;;604      }
;;;605      else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
000022  2804              CMP      r0,#4
000024  d108              BNE      |L38.56|
;;;606      {
;;;607        /* TI2 Configuration */
;;;608        TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
000026  4620              MOV      r0,r4
000028  f7fffffe          BL       TI2_Config
;;;609                   TIM_ICInitStruct->TIM_ICSelection,
;;;610                   TIM_ICInitStruct->TIM_ICFilter);
;;;611    
;;;612        /* Set the Input Capture Prescaler value */
;;;613        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
00002c  88e9              LDRH     r1,[r5,#6]
00002e  4620              MOV      r0,r4
000030  e8bd4070          POP      {r4-r6,lr}
000034  f7ffbffe          B.W      TIM_SetIC2Prescaler
                  |L38.56|
;;;614      }
;;;615      else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
000038  2808              CMP      r0,#8
00003a  8c20              LDRH     r0,[r4,#0x20]
00003c  d117              BNE      |L38.110|
00003e  f4207080          BIC      r0,r0,#0x100
000042  8420              STRH     r0,[r4,#0x20]
000044  8ba6              LDRH     r6,[r4,#0x1c]
000046  8c20              LDRH     r0,[r4,#0x20]
000048  f02606f3          BIC      r6,r6,#0xf3
00004c  ea421303          ORR      r3,r2,r3,LSL #4
000050  f4207000          BIC      r0,r0,#0x200
000054  4333              ORRS     r3,r3,r6
000056  ea402001          ORR      r0,r0,r1,LSL #8
00005a  f4407080          ORR      r0,r0,#0x100
00005e  83a3              STRH     r3,[r4,#0x1c]
000060  8420              STRH     r0,[r4,#0x20]
;;;616      {
;;;617        /* TI3 Configuration */
;;;618        TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
;;;619                   TIM_ICInitStruct->TIM_ICSelection,
;;;620                   TIM_ICInitStruct->TIM_ICFilter);
;;;621    
;;;622        /* Set the Input Capture Prescaler value */
;;;623        TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000062  88e9              LDRH     r1,[r5,#6]
000064  4620              MOV      r0,r4
000066  e8bd4070          POP      {r4-r6,lr}
00006a  f7ffbffe          B.W      TIM_SetIC3Prescaler
                  |L38.110|
00006e  f4205080          BIC      r0,r0,#0x1000
000072  8420              STRH     r0,[r4,#0x20]
000074  8ba6              LDRH     r6,[r4,#0x1c]
000076  8c20              LDRH     r0,[r4,#0x20]
000078  0212              LSLS     r2,r2,#8
00007a  f4264673          BIC      r6,r6,#0xf300
00007e  ea423203          ORR      r2,r2,r3,LSL #12
000082  f4205000          BIC      r0,r0,#0x2000
000086  4332              ORRS     r2,r2,r6
000088  ea403001          ORR      r0,r0,r1,LSL #12
00008c  f4405080          ORR      r0,r0,#0x1000
000090  83a2              STRH     r2,[r4,#0x1c]
000092  8420              STRH     r0,[r4,#0x20]
;;;624      }
;;;625      else
;;;626      {
;;;627        /* TI4 Configuration */
;;;628        TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
;;;629                   TIM_ICInitStruct->TIM_ICSelection,
;;;630                   TIM_ICInitStruct->TIM_ICFilter);
;;;631    
;;;632        /* Set the Input Capture Prescaler value */
;;;633        TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
000094  88e9              LDRH     r1,[r5,#6]
000096  4620              MOV      r0,r4
000098  e8bd4070          POP      {r4-r6,lr}
00009c  f7ffbffe          B.W      TIM_SetIC4Prescaler
;;;634      }
;;;635    }
;;;636    
                          ENDP


                          AREA ||i.TIM_ICStructInit||, CODE, READONLY, ALIGN=1

                  TIM_ICStructInit PROC
;;;788    *******************************************************************************/
;;;789    void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
000000  2100              MOVS     r1,#0
;;;790    {
;;;791      /* Set the default configuration */
;;;792      TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
000002  8001              STRH     r1,[r0,#0]
;;;793      TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
000004  8041              STRH     r1,[r0,#2]
;;;794      TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
000006  2201              MOVS     r2,#1
000008  8082              STRH     r2,[r0,#4]
;;;795      TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
00000a  80c1              STRH     r1,[r0,#6]
;;;796      TIM_ICInitStruct->TIM_ICFilter = 0x00;
00000c  8101              STRH     r1,[r0,#8]
;;;797    }
00000e  4770              BX       lr
;;;798    
                          ENDP


                          AREA ||i.TIM_ITConfig||, CODE, READONLY, ALIGN=1

                  TIM_ITConfig PROC
;;;892    *******************************************************************************/
;;;893    void TIM_ITConfig(TIM_TypeDef* TIMx, u16 TIM_IT, FunctionalState NewState)
000000  2a00              CMP      r2,#0
;;;894    {  
;;;895      /* Check the parameters */
;;;896      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;897      assert_param(IS_TIM_IT(TIM_IT));
;;;898      assert_param(IS_TIM_PERIPH_IT((TIMx), (TIM_IT)));
;;;899      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;900      
;;;901      if (NewState != DISABLE)
;;;902      {
;;;903        /* Enable the Interrupt sources */
;;;904        TIMx->DIER |= TIM_IT;
000002  8982              LDRH     r2,[r0,#0xc]
000004  d001              BEQ      |L40.10|
000006  430a              ORRS     r2,r2,r1
000008  e000              B        |L40.12|
                  |L40.10|
;;;905      }
;;;906      else
;;;907      {
;;;908        /* Disable the Interrupt sources */
;;;909        TIMx->DIER &= (u16)~TIM_IT;
00000a  438a              BICS     r2,r2,r1
                  |L40.12|
00000c  8182              STRH     r2,[r0,#0xc]          ;904
;;;910      }
;;;911    }
00000e  4770              BX       lr
;;;912    
                          ENDP


                          AREA ||i.TIM_ITRxExternalClockConfig||, CODE, READONLY, ALIGN=1

                  TIM_ITRxExternalClockConfig PROC
;;;1037   *******************************************************************************/
;;;1038   void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, u16 TIM_InputTriggerSource)
000000  8902              LDRH     r2,[r0,#8]
000002  f0220270          BIC      r2,r2,#0x70
000006  430a              ORRS     r2,r2,r1
000008  8102              STRH     r2,[r0,#8]
;;;1039   {
;;;1040     /* Check the parameters */
;;;1041     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1042     assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
;;;1043   
;;;1044     /* Select the Internal Trigger */
;;;1045     TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
;;;1046   
;;;1047     /* Select the External clock mode1 */
;;;1048     TIMx->SMCR |= TIM_SlaveMode_External1;
00000a  8901              LDRH     r1,[r0,#8]
00000c  f0410107          ORR      r1,r1,#7
000010  8101              STRH     r1,[r0,#8]
;;;1049   }
000012  4770              BX       lr
;;;1050   /*******************************************************************************
                          ENDP


                          AREA ||i.TIM_InternalClockConfig||, CODE, READONLY, ALIGN=1

                  TIM_InternalClockConfig PROC
;;;1015   *******************************************************************************/
;;;1016   void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
000000  8901              LDRH     r1,[r0,#8]
;;;1017   {
;;;1018     /* Check the parameters */
;;;1019     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1020   
;;;1021     /* Disable slave mode to clock the prescaler directly with the internal clock */
;;;1022     TIMx->SMCR &=  SMCR_SMS_Mask;
000002  f0210107          BIC      r1,r1,#7
000006  8101              STRH     r1,[r0,#8]
;;;1023   }
000008  4770              BX       lr
;;;1024   /*******************************************************************************
                          ENDP


                          AREA ||i.TIM_OC1FastConfig||, CODE, READONLY, ALIGN=1

                  TIM_OC1FastConfig PROC
;;;1782   *******************************************************************************/
;;;1783   void TIM_OC1FastConfig(TIM_TypeDef* TIMx, u16 TIM_OCFast)
000000  8b02              LDRH     r2,[r0,#0x18]
;;;1784   {
;;;1785     u16 tmpccmr1 = 0;
;;;1786   
;;;1787     /* Check the parameters */
;;;1788     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1789     assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
;;;1790   
;;;1791     /* Get the TIMx CCMR1 register value */
;;;1792     tmpccmr1 = TIMx->CCMR1;
;;;1793   
;;;1794     /* Reset the OC1FE Bit */
;;;1795     tmpccmr1 &= CCMR_OC13FE_Reset;
000002  f0220204          BIC      r2,r2,#4
;;;1796   
;;;1797     /* Enable or Disable the Output Compare Fast Bit */
;;;1798     tmpccmr1 |= TIM_OCFast;
000006  430a              ORRS     r2,r2,r1
;;;1799   
;;;1800     /* Write to TIMx CCMR1 */
;;;1801     TIMx->CCMR1 = tmpccmr1;
000008  8302              STRH     r2,[r0,#0x18]
;;;1802   }
00000a  4770              BX       lr
;;;1803   
                          ENDP


                          AREA ||i.TIM_OC1Init||, CODE, READONLY, ALIGN=2

                  TIM_OC1Init PROC
;;;236    *******************************************************************************/
;;;237    void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
000000  b5f0              PUSH     {r4-r7,lr}
;;;238    {
;;;239      u16 tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
;;;240       
;;;241      /* Check the parameters */
;;;242      assert_param(IS_TIM_123458_PERIPH(TIMx)); 
;;;243      assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
;;;244      assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
;;;245      assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
;;;246    
;;;247      /* Disable the Channel 1: Reset the CC1E Bit */
;;;248      TIMx->CCER &= CCER_CC1E_Reset;
000002  8c02              LDRH     r2,[r0,#0x20]
000004  f0220201          BIC      r2,r2,#1
000008  8402              STRH     r2,[r0,#0x20]
;;;249      
;;;250      /* Get the TIMx CCER register value */
;;;251      tmpccer = TIMx->CCER;
00000a  8c05              LDRH     r5,[r0,#0x20]
;;;252    
;;;253      /* Get the TIMx CR2 register value */
;;;254      tmpcr2 =  TIMx->CR2;
00000c  8883              LDRH     r3,[r0,#4]
;;;255      
;;;256      /* Get the TIMx CCMR1 register value */
;;;257      tmpccmrx = TIMx->CCMR1;
00000e  8b02              LDRH     r2,[r0,#0x18]
;;;258        
;;;259      /* Reset the Output Compare Mode Bits */
;;;260      tmpccmrx &= CCMR_OC13M_Mask;
;;;261      
;;;262      /* Select the Output Compare Mode */
;;;263      tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
000010  880c              LDRH     r4,[r1,#0]
000012  f0220270          BIC      r2,r2,#0x70           ;260
;;;264      
;;;265      /* Reset the Output Polarity level */
;;;266      tmpccer &= CCER_CC1P_Reset;
000016  f0250602          BIC      r6,r5,#2
;;;267    
;;;268      /* Set the Output Compare Polarity */
;;;269      tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
00001a  890d              LDRH     r5,[r1,#8]
00001c  4314              ORRS     r4,r4,r2              ;263
;;;270      
;;;271      /* Set the Output State */
;;;272      tmpccer |= TIM_OCInitStruct->TIM_OutputState;
00001e  884a              LDRH     r2,[r1,#2]
000020  4335              ORRS     r5,r5,r6              ;269
000022  432a              ORRS     r2,r2,r5
;;;273      
;;;274      /* Set the Capture Compare Register value */
;;;275      TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
000024  88cf              LDRH     r7,[r1,#6]
;;;276      
;;;277      if((*(u32*)&TIMx == TIM1_BASE) || (*(u32*)&TIMx == TIM8_BASE))
000026  4d0c              LDR      r5,|L44.88|
000028  8687              STRH     r7,[r0,#0x34]