stm32f10x_tim.txt

STM32F103ZET6+UCOSII+UCGUI源码

;;;1416   
;;;1417     /* Reset the OC1M Bits */
;;;1418     tmpccmr1 &= CCMR_OC13M_Mask;
000002  f0220270          BIC      r2,r2,#0x70
;;;1419   
;;;1420     /* Configure The Forced output Mode */
;;;1421     tmpccmr1 |= TIM_ForcedAction;
000006  430a              ORRS     r2,r2,r1
;;;1422   
;;;1423     /* Write to TIMx CCMR1 register */
;;;1424     TIMx->CCMR1 = tmpccmr1;
000008  8302              STRH     r2,[r0,#0x18]
;;;1425   }
00000a  4770              BX       lr
;;;1426   
                          ENDP


                          AREA ||i.TIM_ForcedOC2Config||, CODE, READONLY, ALIGN=1

                  TIM_ForcedOC2Config PROC
;;;1440   *******************************************************************************/
;;;1441   void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
000000  8b02              LDRH     r2,[r0,#0x18]
;;;1442   {
;;;1443     u16 tmpccmr1 = 0;
;;;1444   
;;;1445     /* Check the parameters */
;;;1446     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1447     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1448   
;;;1449     tmpccmr1 = TIMx->CCMR1;
;;;1450   
;;;1451     /* Reset the OC2M Bits */
;;;1452     tmpccmr1 &= CCMR_OC24M_Mask;
000002  f42242e0          BIC      r2,r2,#0x7000
;;;1453   
;;;1454     /* Configure The Forced output Mode */
;;;1455     tmpccmr1 |= (u16)(TIM_ForcedAction << 8);
000006  ea422101          ORR      r1,r2,r1,LSL #8
;;;1456   
;;;1457     /* Write to TIMx CCMR1 register */
;;;1458     TIMx->CCMR1 = tmpccmr1;
00000a  8301              STRH     r1,[r0,#0x18]
;;;1459   }
00000c  4770              BX       lr
;;;1460   
                          ENDP


                          AREA ||i.TIM_ForcedOC3Config||, CODE, READONLY, ALIGN=1

                  TIM_ForcedOC3Config PROC
;;;1474   *******************************************************************************/
;;;1475   void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
000000  8b82              LDRH     r2,[r0,#0x1c]
;;;1476   {
;;;1477     u16 tmpccmr2 = 0;
;;;1478   
;;;1479     /* Check the parameters */
;;;1480     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1481     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1482   
;;;1483     tmpccmr2 = TIMx->CCMR2;
;;;1484   
;;;1485     /* Reset the OC1M Bits */
;;;1486     tmpccmr2 &= CCMR_OC13M_Mask;
000002  f0220270          BIC      r2,r2,#0x70
;;;1487   
;;;1488     /* Configure The Forced output Mode */
;;;1489     tmpccmr2 |= TIM_ForcedAction;
000006  430a              ORRS     r2,r2,r1
;;;1490   
;;;1491     /* Write to TIMx CCMR2 register */
;;;1492     TIMx->CCMR2 = tmpccmr2;
000008  8382              STRH     r2,[r0,#0x1c]
;;;1493   }
00000a  4770              BX       lr
;;;1494   
                          ENDP


                          AREA ||i.TIM_ForcedOC4Config||, CODE, READONLY, ALIGN=1

                  TIM_ForcedOC4Config PROC
;;;1508   *******************************************************************************/
;;;1509   void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
000000  8b82              LDRH     r2,[r0,#0x1c]
;;;1510   {
;;;1511     u16 tmpccmr2 = 0;
;;;1512   
;;;1513     /* Check the parameters */
;;;1514     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1515     assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1516     tmpccmr2 = TIMx->CCMR2;
;;;1517   
;;;1518     /* Reset the OC2M Bits */
;;;1519     tmpccmr2 &= CCMR_OC24M_Mask;
000002  f42242e0          BIC      r2,r2,#0x7000
;;;1520   
;;;1521     /* Configure The Forced output Mode */
;;;1522     tmpccmr2 |= (u16)(TIM_ForcedAction << 8);
000006  ea422101          ORR      r1,r2,r1,LSL #8
;;;1523   
;;;1524     /* Write to TIMx CCMR2 register */
;;;1525     TIMx->CCMR2 = tmpccmr2;
00000a  8381              STRH     r1,[r0,#0x1c]
;;;1526   }
00000c  4770              BX       lr
;;;1527   
                          ENDP


                          AREA ||i.TIM_GenerateEvent||, CODE, READONLY, ALIGN=1

                  TIM_GenerateEvent PROC
;;;927    *******************************************************************************/
;;;928    void TIM_GenerateEvent(TIM_TypeDef* TIMx, u16 TIM_EventSource)
000000  8281              STRH     r1,[r0,#0x14]
;;;929    { 
;;;930      /* Check the parameters */
;;;931      assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;932      assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
;;;933      assert_param(IS_TIM_PERIPH_EVENT((TIMx), (TIM_EventSource)));
;;;934    
;;;935      /* Set the event sources */
;;;936      TIMx->EGR = TIM_EventSource;
;;;937    }
000002  4770              BX       lr
;;;938    
                          ENDP


                          AREA ||i.TIM_GetCapture1||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture1 PROC
;;;2795   *******************************************************************************/
;;;2796   u16 TIM_GetCapture1(TIM_TypeDef* TIMx)
000000  8e80              LDRH     r0,[r0,#0x34]
;;;2797   {
;;;2798     /* Check the parameters */
;;;2799     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;2800   
;;;2801     /* Get the Capture 1 Register value */
;;;2802     return TIMx->CCR1;
;;;2803   }
000002  4770              BX       lr
;;;2804   
                          ENDP


                          AREA ||i.TIM_GetCapture2||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture2 PROC
;;;2812   *******************************************************************************/
;;;2813   u16 TIM_GetCapture2(TIM_TypeDef* TIMx)
000000  8f00              LDRH     r0,[r0,#0x38]
;;;2814   {
;;;2815     /* Check the parameters */
;;;2816     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;2817   
;;;2818     /* Get the Capture 2 Register value */
;;;2819     return TIMx->CCR2;
;;;2820   }
000002  4770              BX       lr
;;;2821   
                          ENDP


                          AREA ||i.TIM_GetCapture3||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture3 PROC
;;;2829   *******************************************************************************/
;;;2830   u16 TIM_GetCapture3(TIM_TypeDef* TIMx)
000000  8f80              LDRH     r0,[r0,#0x3c]
;;;2831   {
;;;2832     /* Check the parameters */
;;;2833     assert_param(IS_TIM_123458_PERIPH(TIMx)); 
;;;2834   
;;;2835     /* Get the Capture 3 Register value */
;;;2836     return TIMx->CCR3;
;;;2837   }
000002  4770              BX       lr
;;;2838   
                          ENDP


                          AREA ||i.TIM_GetCapture4||, CODE, READONLY, ALIGN=1

                  TIM_GetCapture4 PROC
;;;2846   *******************************************************************************/
;;;2847   u16 TIM_GetCapture4(TIM_TypeDef* TIMx)
000000  f8b00040          LDRH     r0,[r0,#0x40]
;;;2848   {
;;;2849     /* Check the parameters */
;;;2850     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;2851   
;;;2852     /* Get the Capture 4 Register value */
;;;2853     return TIMx->CCR4;
;;;2854   }
000004  4770              BX       lr
;;;2855   
                          ENDP


                          AREA ||i.TIM_GetCounter||, CODE, READONLY, ALIGN=1

                  TIM_GetCounter PROC
;;;2862   *******************************************************************************/
;;;2863   u16 TIM_GetCounter(TIM_TypeDef* TIMx)
000000  8c80              LDRH     r0,[r0,#0x24]
;;;2864   {
;;;2865     /* Check the parameters */
;;;2866     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2867   
;;;2868     /* Get the Counter Register value */
;;;2869     return TIMx->CNT;
;;;2870   }
000002  4770              BX       lr
;;;2871   
                          ENDP


                          AREA ||i.TIM_GetFlagStatus||, CODE, READONLY, ALIGN=1

                  TIM_GetFlagStatus PROC
;;;2908   *******************************************************************************/
;;;2909   FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, u16 TIM_FLAG)
000000  4602              MOV      r2,r0
;;;2910   { 
;;;2911     ITStatus bitstatus = RESET;  
;;;2912   
;;;2913     /* Check the parameters */
;;;2914     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2915     assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
;;;2916     assert_param(IS_TIM_PERIPH_FLAG(TIMx, TIM_FLAG));
;;;2917     
;;;2918     if ((TIMx->SR & TIM_FLAG) != (u16)RESET)
000002  8a12              LDRH     r2,[r2,#0x10]
000004  2000              MOVS     r0,#0                 ;2911
000006  420a              TST      r2,r1
000008  d000              BEQ      |L35.12|
;;;2919     {
;;;2920       bitstatus = SET;
00000a  2001              MOVS     r0,#1
                  |L35.12|
;;;2921     }
;;;2922     else
;;;2923     {
;;;2924       bitstatus = RESET;
;;;2925     }
;;;2926     return bitstatus;
;;;2927   }
00000c  4770              BX       lr
;;;2928   
                          ENDP


                          AREA ||i.TIM_GetITStatus||, CODE, READONLY, ALIGN=1

                  TIM_GetITStatus PROC
;;;2978   *******************************************************************************/
;;;2979   ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, u16 TIM_IT)
000000  4602              MOV      r2,r0
;;;2980   {
;;;2981     ITStatus bitstatus = RESET;  
;;;2982     u16 itstatus = 0x0, itenable = 0x0;
;;;2983   
;;;2984     /* Check the parameters */
;;;2985     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2986     assert_param(IS_TIM_GET_IT(TIM_IT));
;;;2987     assert_param(IS_TIM_PERIPH_IT(TIMx, TIM_IT));
;;;2988      
;;;2989     itstatus = TIMx->SR & TIM_IT;
000002  8a13              LDRH     r3,[r2,#0x10]
000004  2000              MOVS     r0,#0                 ;2981
;;;2990     
;;;2991     itenable = TIMx->DIER & TIM_IT;
000006  8992              LDRH     r2,[r2,#0xc]
000008  420b              TST      r3,r1                 ;2989
00000a  ea020201          AND      r2,r2,r1
;;;2992   
;;;2993     if ((itstatus != (u16)RESET) && (itenable != (u16)RESET))
00000e  d002              BEQ      |L36.22|
000010  2a00              CMP      r2,#0
000012  d000              BEQ      |L36.22|
;;;2994     {
;;;2995       bitstatus = SET;
000014  2001              MOVS     r0,#1
                  |L36.22|
;;;2996     }
;;;2997     else
;;;2998     {
;;;2999       bitstatus = RESET;
;;;3000     }
;;;3001     return bitstatus;
;;;3002   }
000016  4770              BX       lr
;;;3003   
                          ENDP


                          AREA ||i.TIM_GetPrescaler||, CODE, READONLY, ALIGN=1

                  TIM_GetPrescaler PROC
;;;2878   *******************************************************************************/
;;;2879   u16 TIM_GetPrescaler(TIM_TypeDef* TIMx)
000000  8d00              LDRH     r0,[r0,#0x28]
;;;2880   {
;;;2881     /* Check the parameters */
;;;2882     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2883   
;;;2884     /* Get the Prescaler Register value */
;;;2885     return TIMx->PSC;
;;;2886   }
000002  4770              BX       lr
;;;2887   
                          ENDP


                          AREA ||i.TIM_ICInit||, CODE, READONLY, ALIGN=1

                  TIM_ICInit PROC
;;;584    *******************************************************************************/
;;;585    void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)