📄 stm32f10x_tim.txt
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000008 14d4 ASRS r4,r2,#19
00000a 4290 CMP r0,r2
00000c d03b BEQ |L20.134|
00000e dc10 BGT |L20.50|
000010 f1b04f80 CMP r0,#0x40000000
000014 d022 BEQ |L20.92|
000016 4926 LDR r1,|L20.176|
000018 1840 ADDS r0,r0,r1
00001a d026 BEQ |L20.106|
00001c 4298 CMP r0,r3
00001e d02b BEQ |L20.120|
000020 42a0 CMP r0,r4
000022 d141 BNE |L20.168|
;;;140 {
;;;141 case TIM1_BASE:
;;;142 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
;;;143 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
;;;144 break;
;;;145
;;;146 case TIM2_BASE:
;;;147 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
;;;148 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
;;;149 break;
;;;150
;;;151 case TIM3_BASE:
;;;152 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
;;;153 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
;;;154 break;
;;;155
;;;156 case TIM4_BASE:
;;;157 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
;;;158 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
;;;159 break;
;;;160
;;;161 case TIM5_BASE:
;;;162 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
000024 2101 MOVS r1,#1
000026 2008 MOVS r0,#8
000028 f7fffffe BL RCC_APB1PeriphResetCmd
;;;163 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
00002c 2100 MOVS r1,#0
00002e 2008 MOVS r0,#8
;;;164 break;
000030 e036 B |L20.160|
|L20.50|
000032 4299 CMP r1,r3 ;139
000034 d02e BEQ |L20.148|
000036 f5b13f8e CMP r1,#0x11c00 ;139
00003a d00d BEQ |L20.88|
00003c f5b13f92 CMP r1,#0x12400 ;139
000040 d132 BNE |L20.168|
;;;165
;;;166 case TIM6_BASE:
;;;167 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
;;;168 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
;;;169 break;
;;;170
;;;171 case TIM7_BASE:
;;;172 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
;;;173 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
;;;174 break;
;;;175
;;;176 case TIM8_BASE:
;;;177 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
000042 2101 MOVS r1,#1
000044 034c LSLS r4,r1,#13
|L20.70|
000046 4620 MOV r0,r4
000048 f7fffffe BL RCC_APB2PeriphResetCmd
;;;178 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
00004c 4620 MOV r0,r4
00004e e8bd4010 POP {r4,lr}
000052 2100 MOVS r1,#0
000054 f7ffbffe B.W RCC_APB2PeriphResetCmd
|L20.88|
000058 2101 MOVS r1,#1 ;142
00005a e7f4 B |L20.70|
|L20.92|
00005c 2101 MOVS r1,#1 ;147
00005e 4608 MOV r0,r1 ;147
000060 f7fffffe BL RCC_APB1PeriphResetCmd
000064 2100 MOVS r1,#0 ;148
000066 2001 MOVS r0,#1 ;148
000068 e01a B |L20.160|
|L20.106|
00006a 2101 MOVS r1,#1 ;152
00006c 2002 MOVS r0,#2 ;152
00006e f7fffffe BL RCC_APB1PeriphResetCmd
000072 2100 MOVS r1,#0 ;153
000074 2002 MOVS r0,#2 ;153
000076 e013 B |L20.160|
|L20.120|
000078 2101 MOVS r1,#1 ;157
00007a 2004 MOVS r0,#4 ;157
00007c f7fffffe BL RCC_APB1PeriphResetCmd
000080 2100 MOVS r1,#0 ;158
000082 2004 MOVS r0,#4 ;158
000084 e00c B |L20.160|
|L20.134|
000086 2101 MOVS r1,#1 ;167
000088 2010 MOVS r0,#0x10 ;167
00008a f7fffffe BL RCC_APB1PeriphResetCmd
00008e 2100 MOVS r1,#0 ;168
000090 2010 MOVS r0,#0x10 ;168
000092 e005 B |L20.160|
|L20.148|
000094 2101 MOVS r1,#1 ;172
000096 2020 MOVS r0,#0x20 ;172
000098 f7fffffe BL RCC_APB1PeriphResetCmd
00009c 2100 MOVS r1,#0 ;173
00009e 2020 MOVS r0,#0x20 ;173
|L20.160|
0000a0 e8bd4010 POP {r4,lr} ;173
0000a4 f7ffbffe B.W RCC_APB1PeriphResetCmd
|L20.168|
;;;179 break;
;;;180
;;;181 default:
;;;182 break;
;;;183 }
;;;184 }
0000a8 bd10 POP {r4,pc}
;;;185
ENDP
0000aa 0000 DCW 0x0000
|L20.172|
DCD 0x40001000
|L20.176|
DCD 0xbffffc00
AREA ||i.TIM_ETRClockMode1Config||, CODE, READONLY, ALIGN=1
TIM_ETRClockMode1Config PROC
;;;1114 *******************************************************************************/
;;;1115 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
000000 b510 PUSH {r4,lr}
;;;1116 u16 ExtTRGFilter)
;;;1117 {
000002 4604 MOV r4,r0
;;;1118 u16 tmpsmcr = 0;
;;;1119
;;;1120 /* Check the parameters */
;;;1121 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1122 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;1123 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;1124 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;1125
;;;1126 /* Configure the ETR Clock source */
;;;1127 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
000004 f7fffffe BL TIM_ETRConfig
;;;1128
;;;1129 /* Get the TIMx SMCR register value */
;;;1130 tmpsmcr = TIMx->SMCR;
000008 8920 LDRH r0,[r4,#8]
;;;1131
;;;1132 /* Reset the SMS Bits */
;;;1133 tmpsmcr &= SMCR_SMS_Mask;
;;;1134 /* Select the External clock mode1 */
;;;1135 tmpsmcr |= TIM_SlaveMode_External1;
;;;1136
;;;1137 /* Select the Trigger selection : ETRF */
;;;1138 tmpsmcr &= SMCR_TS_Mask;
;;;1139 tmpsmcr |= TIM_TS_ETRF;
00000a f0400077 ORR r0,r0,#0x77
;;;1140
;;;1141 /* Write to TIMx SMCR */
;;;1142 TIMx->SMCR = tmpsmcr;
00000e 8120 STRH r0,[r4,#8]
;;;1143 }
000010 bd10 POP {r4,pc}
;;;1144
ENDP
AREA ||i.TIM_ETRClockMode2Config||, CODE, READONLY, ALIGN=1
TIM_ETRClockMode2Config PROC
;;;1164 *******************************************************************************/
;;;1165 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler,
000000 b510 PUSH {r4,lr}
;;;1166 u16 TIM_ExtTRGPolarity, u16 ExtTRGFilter)
;;;1167 {
000002 4604 MOV r4,r0
;;;1168 /* Check the parameters */
;;;1169 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1170 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;1171 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;1172 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;1173
;;;1174 /* Configure the ETR Clock source */
;;;1175 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
000004 f7fffffe BL TIM_ETRConfig
;;;1176
;;;1177 /* Enable the External clock mode2 */
;;;1178 TIMx->SMCR |= SMCR_ECE_Set;
000008 8920 LDRH r0,[r4,#8]
00000a f4404080 ORR r0,r0,#0x4000
00000e 8120 STRH r0,[r4,#8]
;;;1179 }
000010 bd10 POP {r4,pc}
;;;1180
ENDP
AREA ||i.TIM_ETRConfig||, CODE, READONLY, ALIGN=1
TIM_ETRConfig PROC
;;;1200 *******************************************************************************/
;;;1201 void TIM_ETRConfig(TIM_TypeDef* TIMx, u16 TIM_ExtTRGPrescaler, u16 TIM_ExtTRGPolarity,
000000 b510 PUSH {r4,lr}
;;;1202 u16 ExtTRGFilter)
;;;1203 {
;;;1204 u16 tmpsmcr = 0;
;;;1205
;;;1206 /* Check the parameters */
;;;1207 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1208 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
;;;1209 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
;;;1210 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
;;;1211
;;;1212 tmpsmcr = TIMx->SMCR;
000002 8904 LDRH r4,[r0,#8]
;;;1213
;;;1214 /* Reset the ETR Bits */
;;;1215 tmpsmcr &= SMCR_ETR_Mask;
;;;1216
;;;1217 /* Set the Prescaler, the Filter value and the Polarity */
;;;1218 tmpsmcr |= TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | (u16)(ExtTRGFilter << 8);
000004 4311 ORRS r1,r1,r2
000006 b2e4 UXTB r4,r4 ;1215
000008 ea412103 ORR r1,r1,r3,LSL #8
00000c 4321 ORRS r1,r1,r4
;;;1219
;;;1220 /* Write to TIMx SMCR */
;;;1221 TIMx->SMCR = tmpsmcr;
00000e 8101 STRH r1,[r0,#8]
;;;1222 }
000010 bd10 POP {r4,pc}
;;;1223
ENDP
AREA ||i.TIM_EncoderInterfaceConfig||, CODE, READONLY, ALIGN=1
TIM_EncoderInterfaceConfig PROC
;;;1348 *******************************************************************************/
;;;1349 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, u16 TIM_EncoderMode,
000000 b570 PUSH {r4-r6,lr}
;;;1350 u16 TIM_IC1Polarity, u16 TIM_IC2Polarity)
;;;1351 {
;;;1352 u16 tmpsmcr = 0;
;;;1353 u16 tmpccmr1 = 0;
;;;1354 u16 tmpccer = 0;
;;;1355
;;;1356 /* Check the parameters */
;;;1357 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1358 assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
;;;1359 assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
;;;1360 assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
;;;1361
;;;1362 /* Get the TIMx SMCR register value */
;;;1363 tmpsmcr = TIMx->SMCR;
000002 8906 LDRH r6,[r0,#8]
;;;1364
;;;1365 /* Get the TIMx CCMR1 register value */
;;;1366 tmpccmr1 = TIMx->CCMR1;
000004 8b05 LDRH r5,[r0,#0x18]
;;;1367
;;;1368 /* Get the TIMx CCER register value */
;;;1369 tmpccer = TIMx->CCER;
000006 8c04 LDRH r4,[r0,#0x20]
;;;1370
;;;1371 /* Set the encoder Mode */
;;;1372 tmpsmcr &= SMCR_SMS_Mask;
000008 f0260607 BIC r6,r6,#7
;;;1373 tmpsmcr |= TIM_EncoderMode;
00000c 430e ORRS r6,r6,r1
;;;1374
;;;1375 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
;;;1376 tmpccmr1 &= CCMR_CC13S_Mask & CCMR_CC24S_Mask;
00000e f64f41fc MOV r1,#0xfcfc
000012 400d ANDS r5,r5,r1
;;;1377 tmpccmr1 |= CCMR_TI13Direct_Set | CCMR_TI24Direct_Set;
000014 f2401101 MOV r1,#0x101
000018 430d ORRS r5,r5,r1
;;;1378
;;;1379 /* Set the TI1 and the TI2 Polarities */
;;;1380 tmpccer &= CCER_CC1P_Reset & CCER_CC2P_Reset;
00001a f0240422 BIC r4,r4,#0x22
;;;1381 tmpccer |= (TIM_IC1Polarity | (u16)(TIM_IC2Polarity << 4));
00001e ea421103 ORR r1,r2,r3,LSL #4
000022 4321 ORRS r1,r1,r4
;;;1382
;;;1383 /* Write to TIMx SMCR */
;;;1384 TIMx->SMCR = tmpsmcr;
000024 8106 STRH r6,[r0,#8]
;;;1385
;;;1386 /* Write to TIMx CCMR1 */
;;;1387 TIMx->CCMR1 = tmpccmr1;
000026 8305 STRH r5,[r0,#0x18]
;;;1388
;;;1389 /* Write to TIMx CCER */
;;;1390 TIMx->CCER = tmpccer;
000028 8401 STRH r1,[r0,#0x20]
;;;1391 }
00002a bd70 POP {r4-r6,pc}
;;;1392
ENDP
AREA ||i.TIM_ForcedOC1Config||, CODE, READONLY, ALIGN=1
TIM_ForcedOC1Config PROC
;;;1406 *******************************************************************************/
;;;1407 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, u16 TIM_ForcedAction)
000000 8b02 LDRH r2,[r0,#0x18]
;;;1408 {
;;;1409 u16 tmpccmr1 = 0;
;;;1410
;;;1411 /* Check the parameters */
;;;1412 assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;1413 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
;;;1414
;;;1415 tmpccmr1 = TIMx->CCMR1;
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