stm32f10x_tim.txt

STM32F103ZET6+UCOSII+UCGUI源码

; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_tim.o --depend=.\Obj\stm32f10x_tim.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\Config -I..\..\GUI\Core -I..\..\GUI\Font -I..\..\GUI\ConvertColor -I..\..\GUI\AntiAlias -I..\..\GUI\ConvertMono -I..\..\GUI\JPEG -I..\..\GUI\MemDev -I..\..\GUI\MultiLayer -I..\..\GUI\Widget -I..\..\GUI\WM -IC:\Keil\ARM\INC\ST\STM32F10x ..\..\..\FWLib\library\src\stm32f10x_tim.c]
                          THUMB

                          AREA ||i.TI1_Config||, CODE, READONLY, ALIGN=1

                  TI1_Config PROC
;;;3053   *******************************************************************************/
;;;3054   static void TI1_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
000000  b530              PUSH     {r4,r5,lr}
;;;3055                          u16 TIM_ICFilter)
;;;3056   {
;;;3057     u16 tmpccmr1 = 0, tmpccer = 0;
;;;3058   
;;;3059     /* Disable the Channel 1: Reset the CC1E Bit */
;;;3060     TIMx->CCER &= CCER_CC1E_Reset;
000002  8c04              LDRH     r4,[r0,#0x20]
000004  f0240401          BIC      r4,r4,#1
000008  8404              STRH     r4,[r0,#0x20]
;;;3061   
;;;3062     tmpccmr1 = TIMx->CCMR1;
00000a  8b05              LDRH     r5,[r0,#0x18]
;;;3063     tmpccer = TIMx->CCER;
00000c  8c04              LDRH     r4,[r0,#0x20]
;;;3064   
;;;3065     /* Select the Input and set the filter */
;;;3066     tmpccmr1 &= CCMR_CC13S_Mask & CCMR_IC13F_Mask;
;;;3067     tmpccmr1 |= TIM_ICSelection | (u16)(TIM_ICFilter << 4);
00000e  ea421303          ORR      r3,r2,r3,LSL #4
000012  f02505f3          BIC      r5,r5,#0xf3           ;3066
000016  432b              ORRS     r3,r3,r5
;;;3068   
;;;3069     /* Select the Polarity and set the CC1E Bit */
;;;3070     tmpccer &= CCER_CC1P_Reset;
000018  f0240202          BIC      r2,r4,#2
;;;3071     tmpccer |= TIM_ICPolarity | CCER_CC1E_Set;
00001c  430a              ORRS     r2,r2,r1
00001e  f0420101          ORR      r1,r2,#1
;;;3072   
;;;3073     /* Write to TIMx CCMR1 and CCER registers */
;;;3074     TIMx->CCMR1 = tmpccmr1;
000022  8303              STRH     r3,[r0,#0x18]
;;;3075     TIMx->CCER = tmpccer;
000024  8401              STRH     r1,[r0,#0x20]
;;;3076   }
000026  bd30              POP      {r4,r5,pc}
;;;3077   
                          ENDP


                          AREA ||i.TI2_Config||, CODE, READONLY, ALIGN=1

                  TI2_Config PROC
;;;3099   *******************************************************************************/
;;;3100   static void TI2_Config(TIM_TypeDef* TIMx, u16 TIM_ICPolarity, u16 TIM_ICSelection,
000000  b530              PUSH     {r4,r5,lr}
;;;3101                          u16 TIM_ICFilter)
;;;3102   {
;;;3103     u16 tmpccmr1 = 0, tmpccer = 0, tmp = 0;
;;;3104   
;;;3105     /* Disable the Channel 2: Reset the CC2E Bit */
;;;3106     TIMx->CCER &= CCER_CC2E_Reset;
000002  8c04              LDRH     r4,[r0,#0x20]
000004  f0240410          BIC      r4,r4,#0x10
000008  8404              STRH     r4,[r0,#0x20]
;;;3107   
;;;3108     tmpccmr1 = TIMx->CCMR1;
00000a  8b05              LDRH     r5,[r0,#0x18]
;;;3109     tmpccer = TIMx->CCER;
00000c  8c04              LDRH     r4,[r0,#0x20]
;;;3110     tmp = (u16)(TIM_ICPolarity << 4);
;;;3111   
;;;3112     /* Select the Input and set the filter */
;;;3113     tmpccmr1 &= CCMR_CC24S_Mask & CCMR_IC24F_Mask;
00000e  f4254573          BIC      r5,r5,#0xf300
;;;3114     tmpccmr1 |= (u16)(TIM_ICFilter << 12);
000012  ea453303          ORR      r3,r5,r3,LSL #12
;;;3115     tmpccmr1 |= (u16)(TIM_ICSelection << 8);
000016  ea432202          ORR      r2,r3,r2,LSL #8
;;;3116   
;;;3117     /* Select the Polarity and set the CC2E Bit */
;;;3118     tmpccer &= CCER_CC2P_Reset;
00001a  f0240320          BIC      r3,r4,#0x20
;;;3119     tmpccer |=  tmp | CCER_CC2E_Set;
00001e  ea431301          ORR      r3,r3,r1,LSL #4
000022  f0430110          ORR      r1,r3,#0x10
;;;3120   
;;;3121     /* Write to TIMx CCMR1 and CCER registers */
;;;3122     TIMx->CCMR1 = tmpccmr1 ;
000026  8302              STRH     r2,[r0,#0x18]
;;;3123     TIMx->CCER = tmpccer;
000028  8401              STRH     r1,[r0,#0x20]
;;;3124   }
00002a  bd30              POP      {r4,r5,pc}
;;;3125   
                          ENDP


                          AREA ||i.TIM_ARRPreloadConfig||, CODE, READONLY, ALIGN=1

                  TIM_ARRPreloadConfig PROC
;;;1537   *******************************************************************************/
;;;1538   void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;1539   {
;;;1540     /* Check the parameters */
;;;1541     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;1542     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1543   
;;;1544     if (NewState != DISABLE)
;;;1545     {
;;;1546       /* Set the ARR Preload Bit */
;;;1547       TIMx->CR1 |= CR1_ARPE_Set;
000002  8801              LDRH     r1,[r0,#0]
000004  d002              BEQ      |L3.12|
000006  f0410180          ORR      r1,r1,#0x80
00000a  e002              B        |L3.18|
                  |L3.12|
;;;1548     }
;;;1549     else
;;;1550     {
;;;1551       /* Reset the ARR Preload Bit */
;;;1552       TIMx->CR1 &= CR1_ARPE_Reset;
00000c  f240327f          MOV      r2,#0x37f
000010  4011              ANDS     r1,r1,r2
                  |L3.18|
000012  8001              STRH     r1,[r0,#0]            ;1547
;;;1553     }
;;;1554   }
000014  4770              BX       lr
;;;1555   
                          ENDP


                          AREA ||i.TIM_BDTRConfig||, CODE, READONLY, ALIGN=1

                  TIM_BDTRConfig PROC
;;;720    *******************************************************************************/
;;;721    void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;722    {
;;;723      /* Check the parameters */
;;;724      assert_param(IS_TIM_18_PERIPH(TIMx));
;;;725      assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
;;;726      assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
;;;727      assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
;;;728      assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
;;;729      assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
;;;730      assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
;;;731    
;;;732      /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
;;;733         the OSSI State, the dead time value and the Automatic Output Enable Bit */
;;;734    
;;;735      TIMx->BDTR = (u32)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
000002  880a              LDRH     r2,[r1,#0]
000004  884c              LDRH     r4,[r1,#2]
000006  888b              LDRH     r3,[r1,#4]
000008  88cd              LDRH     r5,[r1,#6]
00000a  4322              ORRS     r2,r2,r4
00000c  432b              ORRS     r3,r3,r5
00000e  431a              ORRS     r2,r2,r3
000010  890c              LDRH     r4,[r1,#8]
000012  894b              LDRH     r3,[r1,#0xa]
000014  4322              ORRS     r2,r2,r4
000016  8989              LDRH     r1,[r1,#0xc]
000018  431a              ORRS     r2,r2,r3
00001a  430a              ORRS     r2,r2,r1
00001c  f8a02044          STRH     r2,[r0,#0x44]
;;;736                 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
;;;737                 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
;;;738                 TIM_BDTRInitStruct->TIM_AutomaticOutput;
;;;739    
;;;740    }
000020  bd30              POP      {r4,r5,pc}
;;;741    
                          ENDP


                          AREA ||i.TIM_BDTRStructInit||, CODE, READONLY, ALIGN=1

                  TIM_BDTRStructInit PROC
;;;806    *******************************************************************************/
;;;807    void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
000000  2100              MOVS     r1,#0
;;;808    {
;;;809      /* Set the default configuration */
;;;810      TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
000002  8001              STRH     r1,[r0,#0]
;;;811      TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
000004  8041              STRH     r1,[r0,#2]
;;;812      TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
000006  8081              STRH     r1,[r0,#4]
;;;813      TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
000008  80c1              STRH     r1,[r0,#6]
;;;814      TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
00000a  8101              STRH     r1,[r0,#8]
;;;815      TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
00000c  8141              STRH     r1,[r0,#0xa]
;;;816      TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
00000e  8181              STRH     r1,[r0,#0xc]
;;;817    }
000010  4770              BX       lr
;;;818    
                          ENDP


                          AREA ||i.TIM_CCPreloadControl||, CODE, READONLY, ALIGN=1

                  TIM_CCPreloadControl PROC
;;;1620   *******************************************************************************/
;;;1621   void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;1622   { 
;;;1623     /* Check the parameters */
;;;1624     assert_param(IS_TIM_18_PERIPH(TIMx));
;;;1625     assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;1626   
;;;1627     if (NewState != DISABLE)
;;;1628     {
;;;1629       /* Set the CCPC Bit */
;;;1630       TIMx->CR2 |= CR2_CCPC_Set;
000002  8881              LDRH     r1,[r0,#4]
000004  d002              BEQ      |L6.12|
000006  f0410101          ORR      r1,r1,#1
00000a  e001              B        |L6.16|
                  |L6.12|
;;;1631     }
;;;1632     else
;;;1633     {
;;;1634       /* Reset the CCPC Bit */
;;;1635       TIMx->CR2 &= CR2_CCPC_Reset;
00000c  f0210101          BIC      r1,r1,#1
                  |L6.16|
000010  8081              STRH     r1,[r0,#4]            ;1630
;;;1636     }
;;;1637   }
000012  4770              BX       lr
;;;1638   
                          ENDP


                          AREA ||i.TIM_CCxCmd||, CODE, READONLY, ALIGN=1

                  TIM_CCxCmd PROC
;;;2253   *******************************************************************************/
;;;2254   void TIM_CCxCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCx)
000000  b510              PUSH     {r4,lr}
;;;2255   {
;;;2256     /* Check the parameters */
;;;2257     assert_param(IS_TIM_123458_PERIPH(TIMx));
;;;2258     assert_param(IS_TIM_CHANNEL(TIM_Channel));
;;;2259     assert_param(IS_TIM_CCX(TIM_CCx));
;;;2260   
;;;2261     /* Reset the CCxE Bit */
;;;2262     TIMx->CCER &= (u16)(~((u16)(CCER_CCE_Set << TIM_Channel)));
000002  8c04              LDRH     r4,[r0,#0x20]
000004  2301              MOVS     r3,#1
000006  408b              LSLS     r3,r3,r1
000008  439c              BICS     r4,r4,r3
00000a  8404              STRH     r4,[r0,#0x20]
;;;2263   
;;;2264     /* Set or reset the CCxE Bit */ 
;;;2265     TIMx->CCER |=  (u16)(TIM_CCx << TIM_Channel);
00000c  8c03              LDRH     r3,[r0,#0x20]
00000e  408a              LSLS     r2,r2,r1
000010  4313              ORRS     r3,r3,r2
000012  8403              STRH     r3,[r0,#0x20]
;;;2266   }
000014  bd10              POP      {r4,pc}
;;;2267   
                          ENDP


                          AREA ||i.TIM_CCxNCmd||, CODE, READONLY, ALIGN=1

                  TIM_CCxNCmd PROC
;;;2281   *******************************************************************************/
;;;2282   void TIM_CCxNCmd(TIM_TypeDef* TIMx, u16 TIM_Channel, u16 TIM_CCxN)
000000  b510              PUSH     {r4,lr}
;;;2283   {
;;;2284     /* Check the parameters */
;;;2285     assert_param(IS_TIM_18_PERIPH(TIMx));
;;;2286     assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
;;;2287     assert_param(IS_TIM_CCXN(TIM_CCxN));
;;;2288   
;;;2289     /* Reset the CCxNE Bit */
;;;2290     TIMx->CCER &= (u16)(~((u16)(CCER_CCNE_Set << TIM_Channel)));
000002  8c04              LDRH     r4,[r0,#0x20]
000004  2304              MOVS     r3,#4
000006  408b              LSLS     r3,r3,r1
000008  439c              BICS     r4,r4,r3
00000a  8404              STRH     r4,[r0,#0x20]
;;;2291   
;;;2292     /* Set or reset the CCxNE Bit */ 
;;;2293     TIMx->CCER |=  (u16)(TIM_CCxN << TIM_Channel);
00000c  8c03              LDRH     r3,[r0,#0x20]
00000e  408a              LSLS     r2,r2,r1
000010  4313              ORRS     r3,r3,r2
000012  8403              STRH     r3,[r0,#0x20]
;;;2294   }
000014  bd10              POP      {r4,pc}
;;;2295   
                          ENDP


                          AREA ||i.TIM_ClearFlag||, CODE, READONLY, ALIGN=1

                  TIM_ClearFlag PROC
;;;2949   *******************************************************************************/
;;;2950   void TIM_ClearFlag(TIM_TypeDef* TIMx, u16 TIM_FLAG)
000000  43c9              MVNS     r1,r1
;;;2951   {  
;;;2952     /* Check the parameters */
;;;2953     assert_param(IS_TIM_ALL_PERIPH(TIMx));
;;;2954     assert_param(IS_TIM_CLEAR_FLAG(TIMx, TIM_FLAG));
;;;2955     assert_param(IS_TIM_PERIPH_FLAG(TIMx, TIM_FLAG));
;;;2956      
;;;2957     /* Clear the flags */
;;;2958     TIMx->SR = (u16)~TIM_FLAG;
000002  8201              STRH     r1,[r0,#0x10]
;;;2959   }
000004  4770              BX       lr
;;;2960   
                          ENDP