stm32f10x_usart.txt

STM32F103ZET6+UCOSII+UCGUI源码

000018  e004              B        |L9.36|
                  |L9.26|
;;;921      }
;;;922      else if (usartreg == 0x02) /* The IT  is in CR2 register */
00001a  2b02              CMP      r3,#2
00001c  d101              BNE      |L9.34|
;;;923      {
;;;924        itmask &= USARTx->CR2;
00001e  8a03              LDRH     r3,[r0,#0x10]
000020  e000              B        |L9.36|
                  |L9.34|
;;;925      }
;;;926      else /* The IT  is in CR3 register */
;;;927      {
;;;928        itmask &= USARTx->CR3;
000022  8a83              LDRH     r3,[r0,#0x14]
                  |L9.36|
;;;929      }
;;;930      
;;;931      bitpos = USART_IT >> 0x08;
000024  ea4f2111          LSR      r1,r1,#8
;;;932    
;;;933      bitpos = (u32)0x01 << bitpos;
;;;934      bitpos &= USARTx->SR;
000028  8800              LDRH     r0,[r0,#0]
00002a  4213              TST      r3,r2                 ;924
00002c  fa05f501          LSL      r5,r5,r1              ;933
000030  ea000005          AND      r0,r0,r5
;;;935    
;;;936      if ((itmask != (u16)RESET)&&(bitpos != (u16)RESET))
000034  d001              BEQ      |L9.58|
000036  b100              CBZ      r0,|L9.58|
;;;937      {
;;;938        bitstatus = SET;
000038  2401              MOVS     r4,#1
                  |L9.58|
;;;939      }
;;;940      else
;;;941      {
;;;942        bitstatus = RESET;
;;;943      }
;;;944      
;;;945      return bitstatus;  
00003a  4620              MOV      r0,r4
;;;946    }
00003c  bd70              POP      {r4-r6,pc}
;;;947    
                          ENDP


                          AREA ||i.USART_HalfDuplexCmd||, CODE, READONLY, ALIGN=1

                  USART_HalfDuplexCmd PROC
;;;728    *******************************************************************************/
;;;729    void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;730    {
;;;731      /* Check the parameters */
;;;732      assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;733      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;734      
;;;735      if (NewState != DISABLE)
;;;736      {
;;;737        /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
;;;738        USARTx->CR3 |= CR3_HDSEL_Set;
000002  8a81              LDRH     r1,[r0,#0x14]
000004  d002              BEQ      |L10.12|
000006  f0410108          ORR      r1,r1,#8
00000a  e001              B        |L10.16|
                  |L10.12|
;;;739      }
;;;740      else
;;;741      {
;;;742        /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
;;;743        USARTx->CR3 &= CR3_HDSEL_Reset;
00000c  f0210108          BIC      r1,r1,#8
                  |L10.16|
000010  8281              STRH     r1,[r0,#0x14]         ;738
;;;744      }
;;;745    }
000012  4770              BX       lr
;;;746    
                          ENDP


                          AREA ||i.USART_ITConfig||, CODE, READONLY, ALIGN=1

                  USART_ITConfig PROC
;;;353    *******************************************************************************/
;;;354    void USART_ITConfig(USART_TypeDef* USARTx, u16 USART_IT, FunctionalState NewState)
000000  b510              PUSH     {r4,lr}
;;;355    {
;;;356      u32 usartreg = 0x00, itpos = 0x00, itmask = 0x00;
;;;357      u32 usartxbase = 0x00;
;;;358    
;;;359      /* Check the parameters */
;;;360      assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;361      assert_param(IS_USART_CONFIG_IT(USART_IT));
;;;362      assert_param(IS_USART_PERIPH_IT(USARTx, USART_IT)); /* The CTS interrupt is not available for UART4 and UART5 */     
;;;363      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;364    
;;;365      usartxbase = (*(u32*)&(USARTx));
;;;366    
;;;367      /* Get the USART register index */
;;;368      usartreg = (((u8)USART_IT) >> 0x05);
000002  f3c11342          UBFX     r3,r1,#5,#3
;;;369    
;;;370      /* Get the interrupt position */
;;;371      itpos = USART_IT & IT_Mask;
000006  f001041f          AND      r4,r1,#0x1f
;;;372    
;;;373      itmask = (((u32)0x01) << itpos);
00000a  2101              MOVS     r1,#1
00000c  40a1              LSLS     r1,r1,r4
;;;374        
;;;375      if (usartreg == 0x01) /* The IT is in CR1 register */
00000e  2b01              CMP      r3,#1
000010  d101              BNE      |L11.22|
;;;376      {
;;;377        usartxbase += 0x0C;
000012  300c              ADDS     r0,r0,#0xc
000014  e004              B        |L11.32|
                  |L11.22|
;;;378      }
;;;379      else if (usartreg == 0x02) /* The IT is in CR2 register */
000016  2b02              CMP      r3,#2
000018  d101              BNE      |L11.30|
;;;380      {
;;;381        usartxbase += 0x10;
00001a  3010              ADDS     r0,r0,#0x10
00001c  e000              B        |L11.32|
                  |L11.30|
;;;382      }
;;;383      else /* The IT is in CR3 register */
;;;384      {
;;;385        usartxbase += 0x14; 
00001e  3014              ADDS     r0,r0,#0x14
                  |L11.32|
;;;386      }
;;;387      if (NewState != DISABLE)
000020  2a00              CMP      r2,#0
;;;388      {
;;;389        *(vu32*)usartxbase  |= itmask;
000022  6802              LDR      r2,[r0,#0]
000024  d001              BEQ      |L11.42|
000026  430a              ORRS     r2,r2,r1
000028  e000              B        |L11.44|
                  |L11.42|
;;;390      }
;;;391      else
;;;392      {
;;;393        *(vu32*)usartxbase &= ~itmask;
00002a  438a              BICS     r2,r2,r1
                  |L11.44|
00002c  6002              STR      r2,[r0,#0]            ;389
;;;394      }
;;;395    }
00002e  bd10              POP      {r4,pc}
;;;396    
                          ENDP


                          AREA ||i.USART_Init||, CODE, READONLY, ALIGN=2

                  USART_Init PROC
;;;139    *******************************************************************************/
;;;140    void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;141    {
000002  4604              MOV      r4,r0
;;;142      u32 tmpreg = 0x00, apbclock = 0x00;
;;;143      u32 integerdivider = 0x00;
;;;144      u32 fractionaldivider = 0x00;
;;;145      u32 usartxbase = 0;
;;;146      RCC_ClocksTypeDef RCC_ClocksStatus;
;;;147    
;;;148      /* Check the parameters */
;;;149      assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;150      assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  
;;;151      assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
;;;152      assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
;;;153      assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
;;;154      assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
;;;155      assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
;;;156      /* The hardware flow control is available only for USART1, USART2 and USART3 */          
;;;157      assert_param(IS_USART_PERIPH_HFC(USARTx, USART_InitStruct->USART_HardwareFlowControl));
;;;158      
;;;159      usartxbase = (*(u32*)&USARTx);
;;;160    
;;;161    /*---------------------------- USART CR2 Configuration -----------------------*/
;;;162      tmpreg = USARTx->CR2;
000004  8a00              LDRH     r0,[r0,#0x10]
000006  b085              SUB      sp,sp,#0x14           ;141
000008  460d              MOV      r5,r1                 ;141
;;;163      /* Clear STOP[13:12] bits */
;;;164      tmpreg &= CR2_STOP_CLEAR_Mask;
00000a  f64c71ff          MOV      r1,#0xcfff
00000e  4008              ANDS     r0,r0,r1
;;;165    
;;;166      /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
;;;167      /* Set STOP[13:12] bits according to USART_StopBits value */
;;;168      tmpreg |= (u32)USART_InitStruct->USART_StopBits;
000010  88e9              LDRH     r1,[r5,#6]
000012  4301              ORRS     r1,r1,r0
;;;169      
;;;170      /* Write to USART CR2 */
;;;171      USARTx->CR2 = (u16)tmpreg;
000014  8221              STRH     r1,[r4,#0x10]
;;;172    
;;;173    /*---------------------------- USART CR1 Configuration -----------------------*/
;;;174      tmpreg = USARTx->CR1;
000016  89a0              LDRH     r0,[r4,#0xc]
;;;175      /* Clear M, PCE, PS, TE and RE bits */
;;;176      tmpreg &= CR1_CLEAR_Mask;
000018  f64e11f3          MOV      r1,#0xe9f3
00001c  4008              ANDS     r0,r0,r1
;;;177    
;;;178      /* Configure the USART Word Length, Parity and mode ----------------------- */
;;;179      /* Set the M bits according to USART_WordLength value */
;;;180      /* Set PCE and PS bits according to USART_Parity value */
;;;181      /* Set TE and RE bits according to USART_Mode value */
;;;182      tmpreg |= (u32)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
00001e  88a9              LDRH     r1,[r5,#4]
000020  892a              LDRH     r2,[r5,#8]
000022  4311              ORRS     r1,r1,r2
000024  896a              LDRH     r2,[r5,#0xa]
000026  4302              ORRS     r2,r2,r0
000028  4311              ORRS     r1,r1,r2
;;;183                USART_InitStruct->USART_Mode;
;;;184    
;;;185      /* Write to USART CR1 */
;;;186      USARTx->CR1 = (u16)tmpreg;
00002a  81a1              STRH     r1,[r4,#0xc]
;;;187    
;;;188    /*---------------------------- USART CR3 Configuration -----------------------*/  
;;;189      tmpreg = USARTx->CR3;
00002c  8aa0              LDRH     r0,[r4,#0x14]
;;;190      /* Clear CTSE and RTSE bits */
;;;191      tmpreg &= CR3_CLEAR_Mask;
00002e  f64f41ff          MOV      r1,#0xfcff
000032  4008              ANDS     r0,r0,r1
;;;192    
;;;193      /* Configure the USART HFC -------------------------------------------------*/
;;;194      /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
;;;195      tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
000034  89a9              LDRH     r1,[r5,#0xc]
000036  4301              ORRS     r1,r1,r0
;;;196    
;;;197      /* Write to USART CR3 */
;;;198      USARTx->CR3 = (u16)tmpreg;
000038  82a1              STRH     r1,[r4,#0x14]
;;;199    
;;;200    /*---------------------------- USART BRR Configuration -----------------------*/
;;;201      /* Configure the USART Baud Rate -------------------------------------------*/
;;;202      RCC_GetClocksFreq(&RCC_ClocksStatus);
00003a  4668              MOV      r0,sp
00003c  f7fffffe          BL       RCC_GetClocksFreq
;;;203      if (usartxbase == USART1_BASE)
000040  4811              LDR      r0,|L12.136|
000042  4284              CMP      r4,r0
000044  d101              BNE      |L12.74|
;;;204      {
;;;205        apbclock = RCC_ClocksStatus.PCLK2_Frequency;
000046  9803              LDR      r0,[sp,#0xc]
000048  e000              B        |L12.76|
                  |L12.74|
;;;206      }
;;;207      else
;;;208      {
;;;209        apbclock = RCC_ClocksStatus.PCLK1_Frequency;
00004a  9802              LDR      r0,[sp,#8]
                  |L12.76|
;;;210      }
;;;211    
;;;212      /* Determine the integer part */
;;;213      integerdivider = ((0x19 * apbclock) / (0x04 * (USART_InitStruct->USART_BaudRate)));
;;;214      tmpreg = (integerdivider / 0x64) << 0x04;
00004c  2264              MOVS     r2,#0x64
00004e  eb0001c0          ADD      r1,r0,r0,LSL #3       ;213
000052  eb011000          ADD      r0,r1,r0,LSL #4       ;213
000056  6829              LDR      r1,[r5,#0]            ;213
;;;215    
;;;216      /* Determine the fractional part */
;;;217      fractionaldivider = integerdivider - (0x64 * (tmpreg >> 0x04));
000058  f06f0318          MVN      r3,#0x18
00005c  0089              LSLS     r1,r1,#2              ;213
00005e  fbb0f0f1          UDIV     r0,r0,r1              ;213
000062  fbb0f1f2          UDIV     r1,r0,r2              ;214
000066  0109              LSLS     r1,r1,#4              ;214
000068  090d              LSRS     r5,r1,#4
00006a  435d              MULS     r5,r3,r5
;;;218      tmpreg |= ((((fractionaldivider * 0x10) + 0x32) / 0x64)) & ((u8)0x0F);
00006c  2332              MOVS     r3,#0x32
00006e  eb000085          ADD      r0,r0,r5,LSL #2       ;217
000072  eb031000          ADD      r0,r3,r0,LSL #4
000076  fbb0f0f2          UDIV     r0,r0,r2
00007a  f000000f          AND      r0,r0,#0xf
00007e  4308              ORRS     r0,r0,r1
;;;219    
;;;220      /* Write to USART BRR */
;;;221      USARTx->BRR = (u16)tmpreg;
000080  8120              STRH     r0,[r4,#8]
;;;222    }
000082  b005              ADD      sp,sp,#0x14
000084  bd30              POP      {r4,r5,pc}
;;;223    
                          ENDP

000086  0000              DCW      0x0000
                  |L12.136|
                          DCD      0x40013800

                          AREA ||i.USART_IrDACmd||, CODE, READONLY, ALIGN=1

                  USART_IrDACmd PROC
;;;780    *******************************************************************************/
;;;781    void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;782    {
;;;783      /* Check the parameters */
;;;784      assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;785      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;786        
;;;787      if (NewState != DISABLE)
;;;788      {
;;;789        /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
;;;790        USARTx->CR3 |= CR3_IREN_Set;
000002  8a81              LDRH     r1,[r0,#0x14]
000004  d002              BEQ      |L13.12|
000006  f0410102          ORR      r1,r1,#2
00000a  e001              B        |L13.16|
                  |L13.12|
;;;791      }
;;;792      else
;;;793      {
;;;794        /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
;;;795        USARTx->CR3 &= CR3_IREN_Reset;
00000c  f0210102          BIC      r1,r1,#2
                  |L13.16|
000010  8281              STRH     r1,[r0,#0x14]         ;790
;;;796      }
;;;797    }
000012  4770              BX       lr
;;;798    
                          ENDP


                          AREA ||i.USART_IrDAConfig||, CODE, READONLY, ALIGN=1

                  USART_IrDAConfig PROC
;;;759    *******************************************************************************/
;;;760    void USART_IrDAConfig(USART_TypeDef* USARTx, u16 USART_IrDAMode)
000000  8a82              LDRH     r2,[r0,#0x14]
;;;761    {
;;;762      /* Check the parameters */
;;;763      assert_param(IS_USART_ALL_PERIPH(USARTx));
;;;764      assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
;;;765        
;;;766      USARTx->CR3 &= CR3_IRLP_Mask;
000002  f0220204          BIC      r2,r2,#4
000006  8282              STRH     r2,[r0,#0x14]
;;;767      USARTx->CR3 |= USART_IrDAMode;