📄 stm32f10x_fsmc.txt
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ENDP
AREA ||i.FSMC_NORSRAMStructInit||, CODE, READONLY, ALIGN=1
FSMC_NORSRAMStructInit PROC
;;;356 *******************************************************************************/
;;;357 void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
000000 b510 PUSH {r4,lr}
;;;358 {
;;;359 /* Reset NOR/SRAM Init structure parameters values */
;;;360 FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
000002 2300 MOVS r3,#0
;;;361 FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
000004 2102 MOVS r1,#2
;;;362 FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
000006 e9c03100 STRD r3,r1,[r0,#0]
;;;363 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
00000a 6083 STR r3,[r0,#8]
;;;364 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
00000c 60c3 STR r3,[r0,#0xc]
;;;365 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
00000e 6103 STR r3,[r0,#0x10]
;;;366 FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
000010 6143 STR r3,[r0,#0x14]
;;;367 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
000012 6183 STR r3,[r0,#0x18]
;;;368 FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
000014 02c9 LSLS r1,r1,#11
;;;369 FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
000016 e9c03107 STRD r3,r1,[r0,#0x1c]
00001a 0049 LSLS r1,r1,#1
;;;370 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
;;;371 FSMC_NORSRAMInitStruct->FSMC_AsyncWait = FSMC_AsyncWait_Disable;
00001c e9c01309 STRD r1,r3,[r0,#0x24]
;;;372 FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
000020 62c3 STR r3,[r0,#0x2c]
;;;373 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
000022 6303 STR r3,[r0,#0x30]
000024 6b42 LDR r2,[r0,#0x34]
000026 210f MOVS r1,#0xf
;;;374 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
000028 6011 STR r1,[r2,#0]
00002a 6b42 LDR r2,[r0,#0x34]
;;;375 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
00002c 24ff MOVS r4,#0xff
00002e 6051 STR r1,[r2,#4]
000030 6b42 LDR r2,[r0,#0x34]
;;;376 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
000032 6094 STR r4,[r2,#8]
000034 6b42 LDR r2,[r0,#0x34]
;;;377 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
000036 60d1 STR r1,[r2,#0xc]
000038 6b42 LDR r2,[r0,#0x34]
;;;378 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
00003a 6111 STR r1,[r2,#0x10]
00003c 6b42 LDR r2,[r0,#0x34]
;;;379 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
00003e 6151 STR r1,[r2,#0x14]
000040 6b42 LDR r2,[r0,#0x34]
;;;380 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
000042 6193 STR r3,[r2,#0x18]
000044 6b82 LDR r2,[r0,#0x38]
;;;381 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
000046 6011 STR r1,[r2,#0]
000048 6b82 LDR r2,[r0,#0x38]
;;;382 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
00004a 6051 STR r1,[r2,#4]
00004c 6b82 LDR r2,[r0,#0x38]
;;;383 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
00004e 6094 STR r4,[r2,#8]
000050 6b82 LDR r2,[r0,#0x38]
;;;384 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
000052 60d1 STR r1,[r2,#0xc]
000054 6b82 LDR r2,[r0,#0x38]
;;;385 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
000056 6111 STR r1,[r2,#0x10]
000058 6b82 LDR r2,[r0,#0x38]
;;;386 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
00005a 6151 STR r1,[r2,#0x14]
00005c 6b80 LDR r0,[r0,#0x38]
;;;387 }
00005e 6183 STR r3,[r0,#0x18]
000060 bd10 POP {r4,pc}
;;;388
ENDP
AREA ||i.FSMC_PCCARDCmd||, CODE, READONLY, ALIGN=2
FSMC_PCCARDCmd PROC
;;;528 *******************************************************************************/
;;;529 void FSMC_PCCARDCmd(FunctionalState NewState)
000000 4905 LDR r1,|L16.24|
;;;530 {
;;;531 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;532
;;;533 if (NewState != DISABLE)
000002 2800 CMP r0,#0
;;;534 {
;;;535 /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
;;;536 FSMC_Bank4->PCR4 |= PCR_PBKEN_Set;
000004 6808 LDR r0,[r1,#0]
000006 d002 BEQ |L16.14|
000008 f0400004 ORR r0,r0,#4
00000c e001 B |L16.18|
|L16.14|
;;;537 }
;;;538 else
;;;539 {
;;;540 /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
;;;541 FSMC_Bank4->PCR4 &= PCR_PBKEN_Reset;
00000e 4a03 LDR r2,|L16.28|
000010 4010 ANDS r0,r0,r2
|L16.18|
000012 6008 STR r0,[r1,#0] ;536
;;;542 }
;;;543 }
000014 4770 BX lr
;;;544
ENDP
000016 0000 DCW 0x0000
|L16.24|
DCD 0xa00000a0
|L16.28|
DCD 0x000ffffb
AREA ||i.FSMC_PCCARDDeInit||, CODE, READONLY, ALIGN=2
FSMC_PCCARDDeInit PROC
;;;115 *******************************************************************************/
;;;116 void FSMC_PCCARDDeInit(void)
000000 4805 LDR r0,|L17.24|
;;;117 {
;;;118 /* Set the FSMC_Bank4 registers to their reset values */
;;;119 FSMC_Bank4->PCR4 = 0x00000018;
000002 2118 MOVS r1,#0x18
000004 6001 STR r1,[r0,#0]
;;;120 FSMC_Bank4->SR4 = 0x00000000;
000006 2100 MOVS r1,#0
000008 6041 STR r1,[r0,#4]
;;;121 FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
00000a f04f31fc MOV r1,#0xfcfcfcfc
00000e 6081 STR r1,[r0,#8]
;;;122 FSMC_Bank4->PATT4 = 0xFCFCFCFC;
000010 60c1 STR r1,[r0,#0xc]
;;;123 FSMC_Bank4->PIO4 = 0xFCFCFCFC;
000012 6101 STR r1,[r0,#0x10]
;;;124 }
000014 4770 BX lr
;;;125
ENDP
000016 0000 DCW 0x0000
|L17.24|
DCD 0xa00000a0
AREA ||i.FSMC_PCCARDInit||, CODE, READONLY, ALIGN=2
FSMC_PCCARDInit PROC
;;;299 *******************************************************************************/
;;;300 void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
000000 b570 PUSH {r4-r6,lr}
;;;301 {
;;;302 /* Check the parameters */
;;;303 assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
;;;304 assert_param(IS_FSMC_ADDRESS_LOW_MAPPING(FSMC_PCCARDInitStruct->FSMC_AddressLowMapping));
;;;305 assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
;;;306 assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
;;;307
;;;308
;;;309 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
;;;310 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
;;;311 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
;;;312 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
;;;313
;;;314 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
;;;315 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
;;;316 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
;;;317 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
;;;318
;;;319 assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
;;;320 assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
;;;321 assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
;;;322 assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
;;;323
;;;324 /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
;;;325 FSMC_Bank4->PCR4 = (u32)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
000002 e890000e LDM r0,{r1-r3}
000006 68c4 LDR r4,[r0,#0xc]
000008 4311 ORRS r1,r1,r2
00000a 025b LSLS r3,r3,#9
00000c ea433344 ORR r3,r3,r4,LSL #13
000010 4a13 LDR r2,|L18.96|
000012 4319 ORRS r1,r1,r3
000014 6011 STR r1,[r2,#0]
;;;326 FSMC_PCCARDInitStruct->FSMC_AddressLowMapping |
;;;327 (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
;;;328 (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
;;;329
;;;330 /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
;;;331 FSMC_Bank4->PMEM4 = (u32)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
000016 6901 LDR r1,[r0,#0x10]
000018 e9d13401 LDRD r3,r4,[r1,#4]
00001c 680d LDR r5,[r1,#0]
00001e 68ce LDR r6,[r1,#0xc]
000020 0424 LSLS r4,r4,#16
000022 ea452103 ORR r1,r5,r3,LSL #8
000026 ea446306 ORR r3,r4,r6,LSL #24
00002a 4319 ORRS r1,r1,r3
00002c 6091 STR r1,[r2,#8]
;;;332 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;333 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;334 (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;335
;;;336 /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
;;;337 FSMC_Bank4->PATT4 = (u32)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
00002e 6941 LDR r1,[r0,#0x14]
000030 e9d13401 LDRD r3,r4,[r1,#4]
000034 680d LDR r5,[r1,#0]
000036 68ce LDR r6,[r1,#0xc]
000038 0424 LSLS r4,r4,#16
00003a ea452103 ORR r1,r5,r3,LSL #8
00003e ea446306 ORR r3,r4,r6,LSL #24
000042 4319 ORRS r1,r1,r3
000044 60d1 STR r1,[r2,#0xc]
;;;338 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;339 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;340 (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;341
;;;342 /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
;;;343 FSMC_Bank4->PIO4 = (u32)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
000046 6980 LDR r0,[r0,#0x18]
000048 e9d01301 LDRD r1,r3,[r0,#4]
00004c 6804 LDR r4,[r0,#0]
00004e 68c5 LDR r5,[r0,#0xc]
000050 041b LSLS r3,r3,#16
000052 ea442001 ORR r0,r4,r1,LSL #8
000056 ea436105 ORR r1,r3,r5,LSL #24
00005a 4308 ORRS r0,r0,r1
00005c 6110 STR r0,[r2,#0x10]
;;;344 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;345 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;346 (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;347 }
00005e bd70 POP {r4-r6,pc}
;;;348
ENDP
|L18.96|
DCD 0xa00000a0
AREA ||i.FSMC_PCCARDStructInit||, CODE, READONLY, ALIGN=1
FSMC_PCCARDStructInit PROC
;;;425 *******************************************************************************/
;;;426 void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
000000 2100 MOVS r1,#0
;;;427 {
;;;428 /* Reset PCCARD Init structure parameters values */
;;;429 FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
;;;430 FSMC_PCCARDInitStruct->FSMC_AddressLowMapping = FSMC_AddressLowMapping_Direct;
000002 6001 STR r1,[r0,#0]
;;;431 FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
000004 6041 STR r1,[r0,#4]
;;;432 FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
000006 6081 STR r1,[r0,#8]
;;;433 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
000008 60c1 STR r1,[r0,#0xc]
00000a 6902 LDR r2,[r0,#0x10]
00000c 21fc MOVS r1,#0xfc
;;;434 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00000e 6011 STR r1,[r2,#0]
000010 6902 LDR r2,[r0,#0x10]
;;;435 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
000012 6051 STR r1,[r2,#4]
000014 6902 LDR r2,[r0,#0x10]
;;;436 FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000016 6091 STR r1,[r2,#8]
000018 6902 LDR r2,[r0,#0x10]
;;;437 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00001a 60d1 STR r1,[r2,#0xc]
00001c 6942 LDR r2,[r0,#0x14]
;;;438 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00001e 6011 STR r1,[r2,#0]
000020 6942 LDR r2,[r0,#0x14]
;;;439 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
000022 6051 STR r1,[r2,#4]
000024 6942 LDR r2,[r0,#0x14]
;;;440 FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000026 6091 STR r1,[r2,#8]
000028 6942 LDR r2,[r0,#0x14]
;;;441 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
00002a 60d1 STR r1,[r2,#0xc]
00002c 6982 LDR r2,[r0,#0x18]
;;;442 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
00002e 6011 STR r1,[r2,#0]
000030 6982 LDR r2,[r0,#0x18]
;;;443 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
000032 6051 STR r1,[r2,#4]
000034 6982 LDR r2,[r0,#0x18]
;;;444 FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000036 6091 STR r1,[r2,#8]
000038 6980 LDR r0,[r0,#0x18]
;;;445 }
00003a 60c1 STR r1,[r0,#0xc]
00003c 4770 BX lr
;;;446
ENDP
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