📄 stm32f10x_fsmc.txt
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00005a 66c4 STR r4,[r0,#0x6c]
;;;280 }
;;;281 else
;;;282 {
;;;283 /* FSMC_Bank3_NAND registers configuration */
;;;284 FSMC_Bank3->PCR3 = tmppcr;
;;;285 FSMC_Bank3->PMEM3 = tmppmem;
;;;286 FSMC_Bank3->PATT3 = tmppatt;
;;;287 }
;;;288 }
00005c bd70 POP {r4-r6,pc}
|L10.94|
00005e f8402f80 STR r2,[r0,#0x80]! ;284
000062 6083 STR r3,[r0,#8] ;285
000064 60c4 STR r4,[r0,#0xc] ;286
000066 bd70 POP {r4-r6,pc}
;;;289
ENDP
AREA ||i.FSMC_NANDStructInit||, CODE, READONLY, ALIGN=1
FSMC_NANDStructInit PROC
;;;396 *******************************************************************************/
;;;397 void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
000000 2110 MOVS r1,#0x10
;;;398 {
;;;399 /* Reset NAND Init structure parameters values */
;;;400 FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
;;;401 FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
000002 6001 STR r1,[r0,#0]
000004 2100 MOVS r1,#0
;;;402 FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
000006 6041 STR r1,[r0,#4]
;;;403 FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
000008 6081 STR r1,[r0,#8]
;;;404 FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
00000a 60c1 STR r1,[r0,#0xc]
;;;405 FSMC_NANDInitStruct->FSMC_AddressLowMapping = FSMC_AddressLowMapping_Direct;
00000c 6101 STR r1,[r0,#0x10]
;;;406 FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
00000e 6141 STR r1,[r0,#0x14]
;;;407 FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
000010 6181 STR r1,[r0,#0x18]
;;;408 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
000012 61c1 STR r1,[r0,#0x1c]
000014 6a02 LDR r2,[r0,#0x20]
000016 21fc MOVS r1,#0xfc
;;;409 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
000018 6011 STR r1,[r2,#0]
00001a 6a02 LDR r2,[r0,#0x20]
;;;410 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00001c 6051 STR r1,[r2,#4]
00001e 6a02 LDR r2,[r0,#0x20]
;;;411 FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000020 6091 STR r1,[r2,#8]
000022 6a02 LDR r2,[r0,#0x20]
;;;412 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
000024 60d1 STR r1,[r2,#0xc]
000026 6a42 LDR r2,[r0,#0x24]
;;;413 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
000028 6011 STR r1,[r2,#0]
00002a 6a42 LDR r2,[r0,#0x24]
;;;414 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
00002c 6051 STR r1,[r2,#4]
00002e 6a42 LDR r2,[r0,#0x24]
;;;415 FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
000030 6091 STR r1,[r2,#8]
000032 6a40 LDR r0,[r0,#0x24]
;;;416 }
000034 60c1 STR r1,[r0,#0xc]
000036 4770 BX lr
;;;417
ENDP
AREA ||i.FSMC_NORSRAMCmd||, CODE, READONLY, ALIGN=2
FSMC_NORSRAMCmd PROC
;;;460 *******************************************************************************/
;;;461 void FSMC_NORSRAMCmd(u32 FSMC_Bank, FunctionalState NewState)
000000 f04f4220 MOV r2,#0xa0000000
;;;462 {
;;;463 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
;;;464 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;465
;;;466 if (NewState != DISABLE)
;;;467 {
;;;468 /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
;;;469 FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
000004 eb020080 ADD r0,r2,r0,LSL #2
000008 2900 CMP r1,#0 ;466
00000a 6801 LDR r1,[r0,#0]
00000c d002 BEQ |L12.20|
00000e f0410101 ORR r1,r1,#1
000012 e001 B |L12.24|
|L12.20|
;;;470 }
;;;471 else
;;;472 {
;;;473 /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
;;;474 FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
000014 4a01 LDR r2,|L12.28|
000016 4011 ANDS r1,r1,r2
|L12.24|
000018 6001 STR r1,[r0,#0] ;469
;;;475 }
;;;476 }
00001a 4770 BX lr
;;;477
ENDP
|L12.28|
DCD 0x000ffffe
AREA ||i.FSMC_NORSRAMDeInit||, CODE, READONLY, ALIGN=1
FSMC_NORSRAMDeInit PROC
;;;52 *******************************************************************************/
;;;53 void FSMC_NORSRAMDeInit(u32 FSMC_Bank)
000000 f04f4220 MOV r2,#0xa0000000
;;;54 {
;;;55 /* Check the parameter */
;;;56 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
;;;57
;;;58 /* FSMC_Bank1_NORSRAM1 */
;;;59 if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
;;;60 {
;;;61 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
;;;62 }
;;;63 /* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
;;;64 else
;;;65 {
;;;66 FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
000004 eb020180 ADD r1,r2,r0,LSL #2
000008 b918 CBNZ r0,|L13.18|
00000a f24300db MOV r0,#0x30db ;61
00000e 6010 STR r0,[r2,#0] ;61
000010 e002 B |L13.24|
|L13.18|
000012 f24300d2 MOV r0,#0x30d2
000016 6008 STR r0,[r1,#0]
|L13.24|
;;;67 }
;;;68
;;;69 FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
000018 f06f4070 MVN r0,#0xf0000000
00001c 6048 STR r0,[r1,#4]
;;;70 FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
00001e f8c10104 STR r0,[r1,#0x104]
;;;71 }
000022 4770 BX lr
;;;72
ENDP
AREA ||i.FSMC_NORSRAMInit||, CODE, READONLY, ALIGN=1
FSMC_NORSRAMInit PROC
;;;135 *******************************************************************************/
;;;136 void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
000000 b5f0 PUSH {r4-r7,lr}
;;;137 {
;;;138 /* Check the parameters */
;;;139 assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
;;;140 assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
;;;141 assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
;;;142 assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
;;;143 assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
;;;144 assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
;;;145 assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
;;;146 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
;;;147 assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
;;;148 assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
;;;149 assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
;;;150 assert_param(IS_FSMC_ASYNC_WAIT(FSMC_NORSRAMInitStruct->FSMC_AsyncWait));
;;;151 assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
;;;152 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
;;;153 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
;;;154 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
;;;155 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
;;;156 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
;;;157 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
;;;158 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
;;;159
;;;160 /* Bank1 NOR/SRAM control register configuration */
;;;161 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
000002 e9d04202 LDRD r4,r2,[r0,#8]
000006 6841 LDR r1,[r0,#4]
000008 4321 ORRS r1,r1,r4
00000a e9d03404 LDRD r3,r4,[r0,#0x10]
00000e 431a ORRS r2,r2,r3
000010 4311 ORRS r1,r1,r2
000012 e9d02306 LDRD r2,r3,[r0,#0x18]
000016 4321 ORRS r1,r1,r4
000018 4311 ORRS r1,r1,r2
00001a 4319 ORRS r1,r1,r3
00001c e9d02308 LDRD r2,r3,[r0,#0x20]
000020 4311 ORRS r1,r1,r2
000022 4319 ORRS r1,r1,r3
000024 e9d0230a LDRD r2,r3,[r0,#0x28]
000028 4311 ORRS r1,r1,r2
00002a 4319 ORRS r1,r1,r3
00002c 6b02 LDR r2,[r0,#0x30]
00002e 6803 LDR r3,[r0,#0]
000030 4311 ORRS r1,r1,r2
000032 f04f4220 MOV r2,#0xa0000000
000036 f8421023 STR r1,[r2,r3,LSL #2]
;;;162 (u32)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
;;;163 FSMC_NORSRAMInitStruct->FSMC_MemoryType |
;;;164 FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
;;;165 FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
;;;166 FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
;;;167 FSMC_NORSRAMInitStruct->FSMC_WrapMode |
;;;168 FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
;;;169 FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
;;;170 FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
;;;171 FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
;;;172 FSMC_NORSRAMInitStruct->FSMC_AsyncWait |
;;;173 FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
;;;174
;;;175 if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
00003a 6881 LDR r1,[r0,#8]
00003c 2908 CMP r1,#8
00003e d106 BNE |L14.78|
;;;176 {
;;;177 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (u32)BCR_FACCEN_Set;
000040 6801 LDR r1,[r0,#0]
000042 eb020181 ADD r1,r2,r1,LSL #2
000046 680b LDR r3,[r1,#0]
000048 f0430340 ORR r3,r3,#0x40
00004c 600b STR r3,[r1,#0]
|L14.78|
;;;178 }
;;;179
;;;180 /* Bank1 NOR/SRAM timing register configuration */
;;;181 FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
00004e 6b41 LDR r1,[r0,#0x34]
000050 e9d14301 LDRD r4,r3,[r1,#4]
000054 021d LSLS r5,r3,#8
000056 680b LDR r3,[r1,#0]
000058 e9d16703 LDRD r6,r7,[r1,#0xc]
00005c ea431304 ORR r3,r3,r4,LSL #4
000060 ea454506 ORR r5,r5,r6,LSL #16
000064 432b ORRS r3,r3,r5
000066 ea435507 ORR r5,r3,r7,LSL #20
00006a e9d14305 LDRD r4,r3,[r1,#0x14]
00006e ea456104 ORR r1,r5,r4,LSL #24
000072 6804 LDR r4,[r0,#0]
000074 4319 ORRS r1,r1,r3
000076 eb020384 ADD r3,r2,r4,LSL #2
00007a 6059 STR r1,[r3,#4]
;;;182 (u32)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
;;;183 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
;;;184 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
;;;185 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
;;;186 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
;;;187 (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
;;;188 FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
;;;189
;;;190
;;;191
;;;192 /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
;;;193 if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
00007c 6a81 LDR r1,[r0,#0x28]
00007e f5b14f80 CMP r1,#0x4000
000082 d114 BNE |L14.174|
;;;194 {
;;;195 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
;;;196 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
;;;197 assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
;;;198 assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration));
;;;199 assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
;;;200 assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
;;;201 assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
;;;202
;;;203 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
000084 6b81 LDR r1,[r0,#0x38]
000086 e9d14301 LDRD r4,r3,[r1,#4]
00008a 021d LSLS r5,r3,#8
00008c 680b LDR r3,[r1,#0]
00008e e9d16703 LDRD r6,r7,[r1,#0xc]
000092 ea431304 ORR r3,r3,r4,LSL #4
000096 ea454506 ORR r5,r5,r6,LSL #16
00009a 432b ORRS r3,r3,r5
00009c ea435507 ORR r5,r3,r7,LSL #20
0000a0 e9d14305 LDRD r4,r3,[r1,#0x14]
0000a4 ea456104 ORR r1,r5,r4,LSL #24
0000a8 6800 LDR r0,[r0,#0]
0000aa 4319 ORRS r1,r1,r3
0000ac e002 B |L14.180|
|L14.174|
;;;204 (u32)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
;;;205 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
;;;206 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
;;;207 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
;;;208 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
;;;209 (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
;;;210 FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
;;;211 }
;;;212 else
;;;213 {
;;;214 FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
0000ae 6800 LDR r0,[r0,#0]
0000b0 f06f4170 MVN r1,#0xf0000000
|L14.180|
0000b4 eb020080 ADD r0,r2,r0,LSL #2 ;203
0000b8 f8c01104 STR r1,[r0,#0x104] ;203
;;;215 }
;;;216 }
0000bc bdf0 POP {r4-r7,pc}
;;;217
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