📄 stm32f10x_fsmc.txt
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;;;660 {
;;;661 /* Disable the selected FSMC_Bank2 interrupts */
;;;662 if(FSMC_Bank == FSMC_Bank2_NAND)
;;;663 {
;;;664
;;;665 FSMC_Bank2->SR2 &= (u32)~FSMC_IT;
;;;666 }
;;;667 /* Disable the selected FSMC_Bank3 interrupts */
;;;668 else if (FSMC_Bank == FSMC_Bank3_NAND)
;;;669 {
;;;670 FSMC_Bank3->SR3 &= (u32)~FSMC_IT;
;;;671 }
;;;672 /* Disable the selected FSMC_Bank4 interrupts */
;;;673 else
;;;674 {
;;;675 FSMC_Bank4->SR4 &= (u32)~FSMC_IT;
;;;676 }
;;;677 }
;;;678 }
000026 bd10 POP {r4,pc}
|L6.40|
000028 2810 CMP r0,#0x10 ;662
00002a d103 BNE |L6.52|
00002c 6e58 LDR r0,[r3,#0x64] ;665
00002e 4388 BICS r0,r0,r1 ;665
|L6.48|
000030 6658 STR r0,[r3,#0x64] ;646
000032 bd10 POP {r4,pc}
|L6.52|
000034 42a0 CMP r0,r4 ;668
000036 d101 BNE |L6.60|
000038 3384 ADDS r3,r3,#0x84 ;668
00003a e000 B |L6.62|
|L6.60|
00003c 33a4 ADDS r3,r3,#0xa4 ;670
|L6.62|
00003e 6818 LDR r0,[r3,#0] ;670
000040 4388 BICS r0,r0,r1 ;670
000042 e7ef B |L6.36|
;;;679
ENDP
AREA ||i.FSMC_NANDCmd||, CODE, READONLY, ALIGN=2
FSMC_NANDCmd PROC
;;;489 *******************************************************************************/
;;;490 void FSMC_NANDCmd(u32 FSMC_Bank, FunctionalState NewState)
000000 f04f4220 MOV r2,#0xa0000000
;;;491 {
;;;492 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
;;;493 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;494
;;;495 if (NewState != DISABLE)
000004 b151 CBZ r1,|L7.28|
;;;496 {
;;;497 /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
;;;498 if(FSMC_Bank == FSMC_Bank2_NAND)
000006 2810 CMP r0,#0x10
000008 d103 BNE |L7.18|
;;;499 {
;;;500 FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
00000a 6e10 LDR r0,[r2,#0x60]
00000c f0400004 ORR r0,r0,#4
000010 e009 B |L7.38|
|L7.18|
;;;501 }
;;;502 else
;;;503 {
;;;504 FSMC_Bank3->PCR3 |= PCR_PBKEN_Set;
000012 f8520f80 LDR r0,[r2,#0x80]!
000016 f0400004 ORR r0,r0,#4
00001a e009 B |L7.48|
|L7.28|
;;;505 }
;;;506 }
;;;507 else
;;;508 {
;;;509 /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
;;;510 if(FSMC_Bank == FSMC_Bank2_NAND)
;;;511 {
;;;512 FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
00001c 4905 LDR r1,|L7.52|
00001e 2810 CMP r0,#0x10 ;510
000020 d103 BNE |L7.42|
000022 6e10 LDR r0,[r2,#0x60]
000024 4008 ANDS r0,r0,r1
|L7.38|
000026 6610 STR r0,[r2,#0x60] ;500
;;;513 }
;;;514 else
;;;515 {
;;;516 FSMC_Bank3->PCR3 &= PCR_PBKEN_Reset;
;;;517 }
;;;518 }
;;;519 }
000028 4770 BX lr
|L7.42|
00002a f8520f80 LDR r0,[r2,#0x80]! ;516
00002e 4008 ANDS r0,r0,r1 ;516
|L7.48|
000030 6010 STR r0,[r2,#0] ;504
000032 4770 BX lr
;;;520
ENDP
|L7.52|
DCD 0x000ffffb
AREA ||i.FSMC_NANDDeInit||, CODE, READONLY, ALIGN=1
FSMC_NANDDeInit PROC
;;;83 *******************************************************************************/
;;;84 void FSMC_NANDDeInit(u32 FSMC_Bank)
000000 b510 PUSH {r4,lr}
;;;85 {
;;;86 /* Check the parameter */
;;;87 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
;;;88
;;;89 if(FSMC_Bank == FSMC_Bank2_NAND)
;;;90 {
;;;91 /* Set the FSMC_Bank2 registers to their reset values */
;;;92 FSMC_Bank2->PCR2 = 0x00000018;
000002 2318 MOVS r3,#0x18
;;;93 FSMC_Bank2->SR2 = 0x00000040;
000004 2440 MOVS r4,#0x40
000006 f04f4120 MOV r1,#0xa0000000 ;92
;;;94 FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
00000a f04f32fc MOV r2,#0xfcfcfcfc
00000e 2810 CMP r0,#0x10 ;89
000010 d104 BNE |L8.28|
000012 660b STR r3,[r1,#0x60] ;92
000014 664c STR r4,[r1,#0x64] ;93
000016 668a STR r2,[r1,#0x68]
;;;95 FSMC_Bank2->PATT2 = 0xFCFCFCFC;
000018 66ca STR r2,[r1,#0x6c]
;;;96 }
;;;97 /* FSMC_Bank3_NAND */
;;;98 else
;;;99 {
;;;100 /* Set the FSMC_Bank3 registers to their reset values */
;;;101 FSMC_Bank3->PCR3 = 0x00000018;
;;;102 FSMC_Bank3->SR3 = 0x00000040;
;;;103 FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
;;;104 FSMC_Bank3->PATT3 = 0xFCFCFCFC;
;;;105 }
;;;106 }
00001a bd10 POP {r4,pc}
|L8.28|
00001c f8413f80 STR r3,[r1,#0x80]! ;101
000020 604c STR r4,[r1,#4] ;102
000022 608a STR r2,[r1,#8] ;103
000024 60ca STR r2,[r1,#0xc] ;104
000026 bd10 POP {r4,pc}
;;;107
ENDP
AREA ||i.FSMC_NANDECCCmd||, CODE, READONLY, ALIGN=2
FSMC_NANDECCCmd PROC
;;;556 *******************************************************************************/
;;;557 void FSMC_NANDECCCmd(u32 FSMC_Bank, FunctionalState NewState)
000000 f04f4220 MOV r2,#0xa0000000
;;;558 {
;;;559 assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
;;;560 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;561
;;;562 if (NewState != DISABLE)
000004 b151 CBZ r1,|L9.28|
;;;563 {
;;;564 /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
;;;565 if(FSMC_Bank == FSMC_Bank2_NAND)
000006 2810 CMP r0,#0x10
000008 d103 BNE |L9.18|
;;;566 {
;;;567 FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
00000a 6e10 LDR r0,[r2,#0x60]
00000c f0400040 ORR r0,r0,#0x40
000010 e009 B |L9.38|
|L9.18|
;;;568 }
;;;569 else
;;;570 {
;;;571 FSMC_Bank3->PCR3 |= PCR_ECCEN_Set;
000012 f8520f80 LDR r0,[r2,#0x80]!
000016 f0400040 ORR r0,r0,#0x40
00001a e009 B |L9.48|
|L9.28|
;;;572 }
;;;573 }
;;;574 else
;;;575 {
;;;576 /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
;;;577 if(FSMC_Bank == FSMC_Bank2_NAND)
;;;578 {
;;;579 FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
00001c 4905 LDR r1,|L9.52|
00001e 2810 CMP r0,#0x10 ;577
000020 d103 BNE |L9.42|
000022 6e10 LDR r0,[r2,#0x60]
000024 4008 ANDS r0,r0,r1
|L9.38|
000026 6610 STR r0,[r2,#0x60] ;567
;;;580 }
;;;581 else
;;;582 {
;;;583 FSMC_Bank3->PCR3 &= PCR_ECCEN_Reset;
;;;584 }
;;;585 }
;;;586 }
000028 4770 BX lr
|L9.42|
00002a f8520f80 LDR r0,[r2,#0x80]! ;583
00002e 4008 ANDS r0,r0,r1 ;583
|L9.48|
000030 6010 STR r0,[r2,#0] ;571
000032 4770 BX lr
;;;587
ENDP
|L9.52|
DCD 0x000fffbf
AREA ||i.FSMC_NANDInit||, CODE, READONLY, ALIGN=1
FSMC_NANDInit PROC
;;;227 *******************************************************************************/
;;;228 void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
000000 b570 PUSH {r4-r6,lr}
;;;229 {
;;;230 u32 tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
;;;231
;;;232 /* Check the parameters */
;;;233 assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
;;;234 assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
;;;235 assert_param( IS_FSMC_DATA_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
;;;236 assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
;;;237 assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
;;;238 assert_param( IS_FSMC_ADDRESS_LOW_MAPPING(FSMC_NANDInitStruct->FSMC_AddressLowMapping));
;;;239 assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
;;;240 assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
;;;241
;;;242 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
;;;243 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
;;;244 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
;;;245 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
;;;246
;;;247 assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
;;;248 assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
;;;249 assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
;;;250 assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
;;;251
;;;252 /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
;;;253 tmppcr = (u32)FSMC_NANDInitStruct->FSMC_Waitfeature |
000002 e9d03202 LDRD r3,r2,[r0,#8]
000006 6841 LDR r1,[r0,#4]
000008 4319 ORRS r1,r1,r3
00000a e9d04304 LDRD r4,r3,[r0,#0x10]
00000e 4322 ORRS r2,r2,r4
000010 4311 ORRS r1,r1,r2
000012 4319 ORRS r1,r1,r3
000014 e9d02306 LDRD r2,r3,[r0,#0x18]
000018 ea412242 ORR r2,r1,r2,LSL #9
;;;254 PCR_MemoryType_NAND |
;;;255 FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
;;;256 FSMC_NANDInitStruct->FSMC_ECC |
;;;257 FSMC_NANDInitStruct->FSMC_ECCPageSize |
;;;258 FSMC_NANDInitStruct->FSMC_AddressLowMapping |
;;;259 (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
;;;260 (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
;;;261
;;;262 /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
;;;263 tmppmem = (u32)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
00001c 6a01 LDR r1,[r0,#0x20]
00001e ea423243 ORR r2,r2,r3,LSL #13 ;253
000022 e8910038 LDM r1,{r3-r5}
;;;264 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;265 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;266 (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;267
;;;268 /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
;;;269 tmppatt = (u32)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
000026 68ce LDR r6,[r1,#0xc]
000028 042d LSLS r5,r5,#16 ;263
00002a ea432304 ORR r3,r3,r4,LSL #8 ;263
00002e 6a41 LDR r1,[r0,#0x24]
000030 ea456506 ORR r5,r5,r6,LSL #24 ;263
000034 432b ORRS r3,r3,r5 ;263
000036 e8910070 LDM r1,{r4-r6}
00003a ea442405 ORR r4,r4,r5,LSL #8
00003e 0435 LSLS r5,r6,#16
;;;270 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
;;;271 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
;;;272 (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
;;;273
;;;274 if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
000040 68ce LDR r6,[r1,#0xc]
;;;275 {
;;;276 /* FSMC_Bank2_NAND registers configuration */
;;;277 FSMC_Bank2->PCR2 = tmppcr;
000042 6801 LDR r1,[r0,#0]
000044 ea456506 ORR r5,r5,r6,LSL #24 ;269
000048 432c ORRS r4,r4,r5 ;269
00004a f0420208 ORR r2,r2,#8 ;253
00004e f04f4020 MOV r0,#0xa0000000
000052 2910 CMP r1,#0x10 ;274
000054 d103 BNE |L10.94|
000056 6602 STR r2,[r0,#0x60]
;;;278 FSMC_Bank2->PMEM2 = tmppmem;
000058 6683 STR r3,[r0,#0x68]
;;;279 FSMC_Bank2->PATT2 = tmppatt;
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