stm32f10x_dma.txt

STM32F103ZET6+UCOSII+UCGUI源码

;;;335    {
;;;336      /* Check the parameters */
;;;337      assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;338    
;;;339      /* Return the number of remaining data units for DMAy Channelx */
;;;340      return ((u16)(DMAy_Channelx->CNDTR));
000002  b280              UXTH     r0,r0
;;;341    }
000004  4770              BX       lr
;;;342    
                          ENDP


                          AREA ||i.DMA_GetFlagStatus||, CODE, READONLY, ALIGN=2

                  DMA_GetFlagStatus PROC
;;;398    *******************************************************************************/
;;;399    FlagStatus DMA_GetFlagStatus(u32 DMA_FLAG)
000000  4602              MOV      r2,r0
;;;400    {
;;;401      FlagStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
;;;402      u32 tmpreg = 0;
;;;403    
;;;404      /* Check the parameters */
;;;405      assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
;;;406    
;;;407      /* Calculate the used DMA */
;;;408      if ((DMA_FLAG & FLAG_Mask) != (u32)RESET)
;;;409      {
;;;410        /* Get DMA2 ISR register value */
;;;411        tmpreg = DMA2->ISR ;
000004  4905              LDR      r1,|L6.28|
000006  00d3              LSLS     r3,r2,#3              ;401
000008  d502              BPL      |L6.16|
00000a  f8d11400          LDR      r1,[r1,#0x400]
00000e  e000              B        |L6.18|
                  |L6.16|
;;;412      }
;;;413      else
;;;414      {
;;;415        /* Get DMA1 ISR register value */
;;;416        tmpreg = DMA1->ISR ;
000010  6809              LDR      r1,[r1,#0]
                  |L6.18|
;;;417      }
;;;418    
;;;419      /* Check the status of the specified DMA flag */
;;;420      if ((tmpreg & DMA_FLAG) != (u32)RESET)
000012  4211              TST      r1,r2
000014  d000              BEQ      |L6.24|
;;;421      {
;;;422        /* DMA_FLAG is set */
;;;423        bitstatus = SET;
000016  2001              MOVS     r0,#1
                  |L6.24|
;;;424      }
;;;425      else
;;;426      {
;;;427        /* DMA_FLAG is reset */
;;;428        bitstatus = RESET;
;;;429      }
;;;430      
;;;431      /* Return the DMA_FLAG status */
;;;432      return  bitstatus;
;;;433    }
000018  4770              BX       lr
;;;434    
                          ENDP

00001a  0000              DCW      0x0000
                  |L6.28|
                          DCD      0x40020000

                          AREA ||i.DMA_GetITStatus||, CODE, READONLY, ALIGN=2

                  DMA_GetITStatus PROC
;;;566    *******************************************************************************/
;;;567    ITStatus DMA_GetITStatus(u32 DMA_IT)
000000  4602              MOV      r2,r0
;;;568    {
;;;569      ITStatus bitstatus = RESET;
000002  2000              MOVS     r0,#0
;;;570      u32 tmpreg = 0;
;;;571    
;;;572      /* Check the parameters */
;;;573      assert_param(IS_DMA_GET_IT(DMA_IT));
;;;574    
;;;575      /* Calculate the used DMA */
;;;576      if ((DMA_IT & FLAG_Mask) != (u32)RESET)
;;;577      {
;;;578        /* Get DMA2 ISR register value */
;;;579        tmpreg = DMA2->ISR ;
000004  4905              LDR      r1,|L7.28|
000006  00d3              LSLS     r3,r2,#3              ;569
000008  d502              BPL      |L7.16|
00000a  f8d11400          LDR      r1,[r1,#0x400]
00000e  e000              B        |L7.18|
                  |L7.16|
;;;580      }
;;;581      else
;;;582      {
;;;583        /* Get DMA1 ISR register value */
;;;584        tmpreg = DMA1->ISR ;
000010  6809              LDR      r1,[r1,#0]
                  |L7.18|
;;;585      }
;;;586    
;;;587      /* Check the status of the specified DMA interrupt */
;;;588      if ((tmpreg & DMA_IT) != (u32)RESET)
000012  4211              TST      r1,r2
000014  d000              BEQ      |L7.24|
;;;589      {
;;;590        /* DMA_IT is set */
;;;591        bitstatus = SET;
000016  2001              MOVS     r0,#1
                  |L7.24|
;;;592      }
;;;593      else
;;;594      {
;;;595        /* DMA_IT is reset */
;;;596        bitstatus = RESET;
;;;597      }
;;;598      /* Return the DMA_IT status */
;;;599      return  bitstatus;
;;;600    }
000018  4770              BX       lr
;;;601    
                          ENDP

00001a  0000              DCW      0x0000
                  |L7.28|
                          DCD      0x40020000

                          AREA ||i.DMA_ITConfig||, CODE, READONLY, ALIGN=1

                  DMA_ITConfig PROC
;;;303    *******************************************************************************/
;;;304    void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, u32 DMA_IT, FunctionalState NewState)
000000  2a00              CMP      r2,#0
;;;305    {
;;;306      /* Check the parameters */
;;;307      assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;308      assert_param(IS_DMA_CONFIG_IT(DMA_IT));
;;;309      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;310    
;;;311      if (NewState != DISABLE)
;;;312      {
;;;313        /* Enable the selected DMA interrupts */
;;;314        DMAy_Channelx->CCR |= DMA_IT;
000002  6802              LDR      r2,[r0,#0]
000004  d001              BEQ      |L8.10|
000006  430a              ORRS     r2,r2,r1
000008  e000              B        |L8.12|
                  |L8.10|
;;;315      }
;;;316      else
;;;317      {
;;;318        /* Disable the selected DMA interrupts */
;;;319        DMAy_Channelx->CCR &= ~DMA_IT;
00000a  438a              BICS     r2,r2,r1
                  |L8.12|
00000c  6002              STR      r2,[r0,#0]            ;314
;;;320      }
;;;321    }
00000e  4770              BX       lr
;;;322    
                          ENDP


                          AREA ||i.DMA_Init||, CODE, READONLY, ALIGN=1

                  DMA_Init PROC
;;;162    ******************************************************************************/
;;;163    void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
000000  b570              PUSH     {r4-r6,lr}
;;;164    {
;;;165      u32 tmpreg = 0;
;;;166    
;;;167      /* Check the parameters */
;;;168      assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;169      assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
;;;170      assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
;;;171      assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
;;;172      assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));   
;;;173      assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
;;;174      assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
;;;175      assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
;;;176      assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
;;;177      assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
;;;178    
;;;179    /*--------------------------- DMAy Channelx CCR Configuration -----------------*/
;;;180      /* Get the DMAy_Channelx CCR value */
;;;181      tmpreg = DMAy_Channelx->CCR;
000002  6802              LDR      r2,[r0,#0]
;;;182      /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
;;;183      tmpreg &= CCR_CLEAR_Mask;
000004  f64773f0          MOV      r3,#0x7ff0
000008  439a              BICS     r2,r2,r3
;;;184      /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
;;;185      /* Set DIR bit according to DMA_DIR value */
;;;186      /* Set CIRC bit according to DMA_Mode value */
;;;187      /* Set PINC bit according to DMA_PeripheralInc value */
;;;188      /* Set MINC bit according to DMA_MemoryInc value */
;;;189      /* Set PSIZE bits according to DMA_PeripheralDataSize value */
;;;190      /* Set MSIZE bits according to DMA_MemoryDataSize value */
;;;191      /* Set PL bits according to DMA_Priority value */
;;;192      /* Set the MEM2MEM bit according to DMA_M2M value */
;;;193      tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
00000a  6a0d              LDR      r5,[r1,#0x20]
00000c  688b              LDR      r3,[r1,#8]
00000e  690c              LDR      r4,[r1,#0x10]
000010  432b              ORRS     r3,r3,r5
000012  e9d16505          LDRD     r6,r5,[r1,#0x14]
000016  4334              ORRS     r4,r4,r6
000018  4323              ORRS     r3,r3,r4
00001a  69cc              LDR      r4,[r1,#0x1c]
00001c  432b              ORRS     r3,r3,r5
00001e  4323              ORRS     r3,r3,r4
000020  e9d15409          LDRD     r5,r4,[r1,#0x24]
000024  432b              ORRS     r3,r3,r5
000026  4323              ORRS     r3,r3,r4
000028  4313              ORRS     r3,r3,r2
;;;194                DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
;;;195                DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
;;;196                DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
;;;197      /* Write to DMAy Channelx CCR */
;;;198      DMAy_Channelx->CCR = tmpreg;
00002a  6003              STR      r3,[r0,#0]
;;;199    
;;;200    /*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
;;;201      /* Write to DMAy Channelx CNDTR */
;;;202      DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
00002c  68ca              LDR      r2,[r1,#0xc]
00002e  6042              STR      r2,[r0,#4]
;;;203    
;;;204    /*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
;;;205      /* Write to DMAy Channelx CPAR */
;;;206      DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
000030  680a              LDR      r2,[r1,#0]
000032  6082              STR      r2,[r0,#8]
;;;207    
;;;208    /*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
;;;209      /* Write to DMAy Channelx CMAR */
;;;210      DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
000034  6849              LDR      r1,[r1,#4]
000036  60c1              STR      r1,[r0,#0xc]
;;;211    }
000038  bd70              POP      {r4-r6,pc}
;;;212    
                          ENDP


                          AREA ||i.DMA_StructInit||, CODE, READONLY, ALIGN=1

                  DMA_StructInit PROC
;;;220    *******************************************************************************/
;;;221    void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
000000  2100              MOVS     r1,#0
;;;222    {
;;;223    /*-------------- Reset DMA init structure parameters values ------------------*/
;;;224      /* Initialize the DMA_PeripheralBaseAddr member */
;;;225      DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
;;;226    
;;;227      /* Initialize the DMA_MemoryBaseAddr member */
;;;228      DMA_InitStruct->DMA_MemoryBaseAddr = 0;
000002  6001              STR      r1,[r0,#0]
;;;229    
;;;230      /* Initialize the DMA_DIR member */
;;;231      DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
000004  6041              STR      r1,[r0,#4]
;;;232    
;;;233      /* Initialize the DMA_BufferSize member */
;;;234      DMA_InitStruct->DMA_BufferSize = 0;
000006  6081              STR      r1,[r0,#8]
;;;235    
;;;236      /* Initialize the DMA_PeripheralInc member */
;;;237      DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
000008  60c1              STR      r1,[r0,#0xc]
;;;238    
;;;239      /* Initialize the DMA_MemoryInc member */
;;;240      DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
00000a  6101              STR      r1,[r0,#0x10]
;;;241    
;;;242      /* Initialize the DMA_PeripheralDataSize member */
;;;243      DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
00000c  6141              STR      r1,[r0,#0x14]
;;;244    
;;;245      /* Initialize the DMA_MemoryDataSize member */
;;;246      DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
00000e  6181              STR      r1,[r0,#0x18]
;;;247    
;;;248      /* Initialize the DMA_Mode member */
;;;249      DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
000010  61c1              STR      r1,[r0,#0x1c]
;;;250    
;;;251      /* Initialize the DMA_Priority member */
;;;252      DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
000012  6201              STR      r1,[r0,#0x20]
;;;253    
;;;254      /* Initialize the DMA_M2M member */
;;;255      DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
000014  6241              STR      r1,[r0,#0x24]
;;;256    }
000016  6281              STR      r1,[r0,#0x28]
000018  4770              BX       lr
;;;257    
                          ENDP