📄 stm32f10x_dma.txt
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; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_dma.o --depend=.\Obj\stm32f10x_dma.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\Config -I..\..\GUI\Core -I..\..\GUI\Font -I..\..\GUI\ConvertColor -I..\..\GUI\AntiAlias -I..\..\GUI\ConvertMono -I..\..\GUI\JPEG -I..\..\GUI\MemDev -I..\..\GUI\MultiLayer -I..\..\GUI\Widget -I..\..\GUI\WM -IC:\Keil\ARM\INC\ST\STM32F10x ..\..\..\FWLib\library\src\stm32f10x_dma.c]
THUMB
AREA ||i.DMA_ClearFlag||, CODE, READONLY, ALIGN=2
DMA_ClearFlag PROC
;;;491 *******************************************************************************/
;;;492 void DMA_ClearFlag(u32 DMA_FLAG)
000000 4903 LDR r1,|L1.16|
;;;493 {
000002 00c2 LSLS r2,r0,#3
;;;494 /* Check the parameters */
;;;495 assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
;;;496
;;;497 /* Calculate the used DMA */
;;;498 if ((DMA_FLAG & FLAG_Mask) != (u32)RESET)
000004 d502 BPL |L1.12|
;;;499 {
;;;500 /* Clear the selected DMA flags */
;;;501 DMA2->IFCR = DMA_FLAG;
000006 f8c10404 STR r0,[r1,#0x404]
;;;502 }
;;;503 else
;;;504 {
;;;505 /* Clear the selected DMA flags */
;;;506 DMA1->IFCR = DMA_FLAG;
;;;507 }
;;;508 }
00000a 4770 BX lr
|L1.12|
00000c 6048 STR r0,[r1,#4] ;506
00000e 4770 BX lr
;;;509
ENDP
|L1.16|
DCD 0x40020000
AREA ||i.DMA_ClearITPendingBit||, CODE, READONLY, ALIGN=2
DMA_ClearITPendingBit PROC
;;;658 *******************************************************************************/
;;;659 void DMA_ClearITPendingBit(u32 DMA_IT)
000000 4903 LDR r1,|L2.16|
;;;660 {
000002 00c2 LSLS r2,r0,#3
;;;661 /* Check the parameters */
;;;662 assert_param(IS_DMA_CLEAR_IT(DMA_IT));
;;;663
;;;664 /* Calculate the used DMA */
;;;665 if ((DMA_IT & FLAG_Mask) != (u32)RESET)
000004 d502 BPL |L2.12|
;;;666 {
;;;667 /* Clear the selected DMA interrupt pending bits */
;;;668 DMA2->IFCR = DMA_IT;
000006 f8c10404 STR r0,[r1,#0x404]
;;;669 }
;;;670 else
;;;671 {
;;;672 /* Clear the selected DMA interrupt pending bits */
;;;673 DMA1->IFCR = DMA_IT;
;;;674 }
;;;675 }
00000a 4770 BX lr
|L2.12|
00000c 6048 STR r0,[r1,#4] ;673
00000e 4770 BX lr
;;;676
ENDP
|L2.16|
DCD 0x40020000
AREA ||i.DMA_Cmd||, CODE, READONLY, ALIGN=1
DMA_Cmd PROC
;;;268 *******************************************************************************/
;;;269 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
000000 2900 CMP r1,#0
;;;270 {
;;;271 /* Check the parameters */
;;;272 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;273 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;274
;;;275 if (NewState != DISABLE)
;;;276 {
;;;277 /* Enable the selected DMAy Channelx */
;;;278 DMAy_Channelx->CCR |= CCR_ENABLE_Set;
000002 6801 LDR r1,[r0,#0]
000004 d002 BEQ |L3.12|
000006 f0410101 ORR r1,r1,#1
00000a e001 B |L3.16|
|L3.12|
;;;279 }
;;;280 else
;;;281 {
;;;282 /* Disable the selected DMAy Channelx */
;;;283 DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
00000c f0210101 BIC r1,r1,#1
|L3.16|
000010 6001 STR r1,[r0,#0] ;278
;;;284 }
;;;285 }
000012 4770 BX lr
;;;286
ENDP
AREA ||i.DMA_DeInit||, CODE, READONLY, ALIGN=2
DMA_DeInit PROC
;;;62 *******************************************************************************/
;;;63 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
000000 6802 LDR r2,[r0,#0]
;;;64 {
;;;65 /* Check the parameters */
;;;66 assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
;;;67
;;;68 /* Disable the selected DMAy Channelx */
;;;69 DMAy_Channelx->CCR &= CCR_ENABLE_Reset;
;;;70
;;;71 /* Reset DMAy Channelx control register */
;;;72 DMAy_Channelx->CCR = 0;
000002 2100 MOVS r1,#0
000004 f0220201 BIC r2,r2,#1 ;69
000008 6002 STR r2,[r0,#0] ;69
00000a 6001 STR r1,[r0,#0]
;;;73
;;;74 /* Reset DMAy Channelx remaining bytes register */
;;;75 DMAy_Channelx->CNDTR = 0;
00000c 6041 STR r1,[r0,#4]
;;;76
;;;77 /* Reset DMAy Channelx peripheral address register */
;;;78 DMAy_Channelx->CPAR = 0;
00000e 6081 STR r1,[r0,#8]
;;;79
;;;80 /* Reset DMAy Channelx memory address register */
;;;81 DMAy_Channelx->CMAR = 0;
000010 60c1 STR r1,[r0,#0xc]
;;;82
;;;83 switch (*(u32*)&DMAy_Channelx)
000012 4b30 LDR r3,|L4.212|
;;;84 {
;;;85 case DMA1_Channel1_BASE:
;;;86 /* Reset interrupt pending bits for DMA1 Channel1 */
;;;87 DMA1->IFCR |= DMA1_Channel1_IT_Mask;
000014 492f LDR r1,|L4.212|
000016 1ac2 SUBS r2,r0,r3 ;83
000018 3980 SUBS r1,r1,#0x80
00001a 4298 CMP r0,r3 ;83
00001c d045 BEQ |L4.170|
00001e dc18 BGT |L4.82|
000020 4b2d LDR r3,|L4.216|
000022 eba00203 SUB r2,r0,r3 ;83
000026 4298 CMP r0,r3 ;83
000028 d037 BEQ |L4.154|
00002a dc0a BGT |L4.66|
00002c 4a2b LDR r2,|L4.220|
00002e 1880 ADDS r0,r0,r2 ;83
000030 d02b BEQ |L4.138|
000032 2814 CMP r0,#0x14 ;83
000034 d02d BEQ |L4.146|
000036 2828 CMP r0,#0x28 ;83
000038 d126 BNE |L4.136|
;;;88 break;
;;;89
;;;90 case DMA1_Channel2_BASE:
;;;91 /* Reset interrupt pending bits for DMA1 Channel2 */
;;;92 DMA1->IFCR |= DMA1_Channel2_IT_Mask;
;;;93 break;
;;;94
;;;95 case DMA1_Channel3_BASE:
;;;96 /* Reset interrupt pending bits for DMA1 Channel3 */
;;;97 DMA1->IFCR |= DMA1_Channel3_IT_Mask;
00003a 6848 LDR r0,[r1,#4]
00003c f4406070 ORR r0,r0,#0xf00
;;;98 break;
000040 e036 B |L4.176|
|L4.66|
000042 2a14 CMP r2,#0x14 ;83
000044 d02d BEQ |L4.162|
000046 2a28 CMP r2,#0x28 ;83
000048 d11e BNE |L4.136|
;;;99
;;;100 case DMA1_Channel4_BASE:
;;;101 /* Reset interrupt pending bits for DMA1 Channel4 */
;;;102 DMA1->IFCR |= DMA1_Channel4_IT_Mask;
;;;103 break;
;;;104
;;;105 case DMA1_Channel5_BASE:
;;;106 /* Reset interrupt pending bits for DMA1 Channel5 */
;;;107 DMA1->IFCR |= DMA1_Channel5_IT_Mask;
;;;108 break;
;;;109
;;;110 case DMA1_Channel6_BASE:
;;;111 /* Reset interrupt pending bits for DMA1 Channel6 */
;;;112 DMA1->IFCR |= DMA1_Channel6_IT_Mask;
00004a 6848 LDR r0,[r1,#4]
00004c f4400070 ORR r0,r0,#0xf00000
;;;113 break;
000050 e02e B |L4.176|
|L4.82|
000052 f5b27f6c CMP r2,#0x3b0 ;83
000056 d032 BEQ |L4.190|
000058 dc0a BGT |L4.112|
00005a f5b27f62 CMP r2,#0x388 ;83
00005e d029 BEQ |L4.180|
000060 f5b27f67 CMP r2,#0x39c ;83
000064 d110 BNE |L4.136|
;;;114
;;;115 case DMA1_Channel7_BASE:
;;;116 /* Reset interrupt pending bits for DMA1 Channel7 */
;;;117 DMA1->IFCR |= DMA1_Channel7_IT_Mask;
;;;118 break;
;;;119
;;;120 case DMA2_Channel1_BASE:
;;;121 /* Reset interrupt pending bits for DMA2 Channel1 */
;;;122 DMA2->IFCR |= DMA2_Channel1_IT_Mask;
;;;123 break;
;;;124
;;;125 case DMA2_Channel2_BASE:
;;;126 /* Reset interrupt pending bits for DMA2 Channel2 */
;;;127 DMA2->IFCR |= DMA2_Channel2_IT_Mask;
000066 f8d10404 LDR r0,[r1,#0x404]
00006a f04000f0 ORR r0,r0,#0xf0
;;;128 break;
00006e e009 B |L4.132|
|L4.112|
000070 f5b27f71 CMP r2,#0x3c4 ;83
000074 d028 BEQ |L4.200|
000076 f5b27f76 CMP r2,#0x3d8 ;83
00007a d105 BNE |L4.136|
;;;129
;;;130 case DMA2_Channel3_BASE:
;;;131 /* Reset interrupt pending bits for DMA2 Channel3 */
;;;132 DMA2->IFCR |= DMA2_Channel3_IT_Mask;
;;;133 break;
;;;134
;;;135 case DMA2_Channel4_BASE:
;;;136 /* Reset interrupt pending bits for DMA2 Channel4 */
;;;137 DMA2->IFCR |= DMA2_Channel4_IT_Mask;
;;;138 break;
;;;139
;;;140 case DMA2_Channel5_BASE:
;;;141 /* Reset interrupt pending bits for DMA2 Channel5 */
;;;142 DMA2->IFCR |= DMA2_Channel5_IT_Mask;
00007c f8d10404 LDR r0,[r1,#0x404]
000080 f4402070 ORR r0,r0,#0xf0000
|L4.132|
000084 f8c10404 STR r0,[r1,#0x404]
|L4.136|
;;;143 break;
;;;144
;;;145 default:
;;;146 break;
;;;147 }
;;;148 }
000088 4770 BX lr
|L4.138|
00008a 6848 LDR r0,[r1,#4] ;87
00008c f040000f ORR r0,r0,#0xf ;87
000090 e00e B |L4.176|
|L4.146|
000092 6848 LDR r0,[r1,#4] ;92
000094 f04000f0 ORR r0,r0,#0xf0 ;92
000098 e00a B |L4.176|
|L4.154|
00009a 6848 LDR r0,[r1,#4] ;102
00009c f4404070 ORR r0,r0,#0xf000 ;102
0000a0 e006 B |L4.176|
|L4.162|
0000a2 6848 LDR r0,[r1,#4] ;107
0000a4 f4402070 ORR r0,r0,#0xf0000 ;107
0000a8 e002 B |L4.176|
|L4.170|
0000aa 6848 LDR r0,[r1,#4] ;117
0000ac f0406070 ORR r0,r0,#0xf000000 ;117
|L4.176|
0000b0 6048 STR r0,[r1,#4] ;117
0000b2 4770 BX lr
|L4.180|
0000b4 f8d10404 LDR r0,[r1,#0x404] ;122
0000b8 f040000f ORR r0,r0,#0xf ;122
0000bc e7e2 B |L4.132|
|L4.190|
0000be f8d10404 LDR r0,[r1,#0x404] ;132
0000c2 f4406070 ORR r0,r0,#0xf00 ;132
0000c6 e7dd B |L4.132|
|L4.200|
0000c8 f8d10404 LDR r0,[r1,#0x404] ;137
0000cc f4404070 ORR r0,r0,#0xf000 ;137
0000d0 e7d8 B |L4.132|
;;;149
ENDP
0000d2 0000 DCW 0x0000
|L4.212|
DCD 0x40020080
|L4.216|
DCD 0x40020044
|L4.220|
DCD 0xbffdfff8
AREA ||i.DMA_GetCurrDataCounter||, CODE, READONLY, ALIGN=1
DMA_GetCurrDataCounter PROC
;;;333 *******************************************************************************/
;;;334 u16 DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
000000 6840 LDR r0,[r0,#4]
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