📄 stm32f10x_rcc.txt
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;;;1026 return bitstatus;
;;;1027 }
000028 4770 BX lr
;;;1028
ENDP
00002a 0000 DCW 0x0000
|L14.44|
DCD 0x40021000
AREA ||i.RCC_GetITStatus||, CODE, READONLY, ALIGN=2
RCC_GetITStatus PROC
;;;1058 *******************************************************************************/
;;;1059 ITStatus RCC_GetITStatus(u8 RCC_IT)
000000 4903 LDR r1,|L15.16|
;;;1060 {
000002 4602 MOV r2,r0
;;;1061 ITStatus bitstatus = RESET;
;;;1062
;;;1063 /* Check the parameters */
;;;1064 assert_param(IS_RCC_GET_IT(RCC_IT));
;;;1065
;;;1066 /* Check the status of the specified RCC interrupt */
;;;1067 if ((RCC->CIR & RCC_IT) != (u32)RESET)
000004 6889 LDR r1,[r1,#8]
000006 2000 MOVS r0,#0 ;1061
000008 4211 TST r1,r2
00000a d000 BEQ |L15.14|
;;;1068 {
;;;1069 bitstatus = SET;
00000c 2001 MOVS r0,#1
|L15.14|
;;;1070 }
;;;1071 else
;;;1072 {
;;;1073 bitstatus = RESET;
;;;1074 }
;;;1075
;;;1076 /* Return the RCC_IT status */
;;;1077 return bitstatus;
;;;1078 }
00000e 4770 BX lr
;;;1079
ENDP
|L15.16|
DCD 0x40021000
AREA ||i.RCC_GetSYSCLKSource||, CODE, READONLY, ALIGN=2
RCC_GetSYSCLKSource PROC
;;;363 *******************************************************************************/
;;;364 u8 RCC_GetSYSCLKSource(void)
000000 4802 LDR r0,|L16.12|
;;;365 {
;;;366 return ((u8)(RCC->CFGR & CFGR_SWS_Mask));
000002 6840 LDR r0,[r0,#4]
000004 f000000c AND r0,r0,#0xc
;;;367 }
000008 4770 BX lr
;;;368
ENDP
00000a 0000 DCW 0x0000
|L16.12|
DCD 0x40021000
AREA ||i.RCC_HCLKConfig||, CODE, READONLY, ALIGN=2
RCC_HCLKConfig PROC
;;;386 *******************************************************************************/
;;;387 void RCC_HCLKConfig(u32 RCC_SYSCLK)
000000 4a03 LDR r2,|L17.16|
;;;388 {
;;;389 u32 tmpreg = 0;
;;;390
;;;391 /* Check the parameters */
;;;392 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
;;;393
;;;394 tmpreg = RCC->CFGR;
000002 6851 LDR r1,[r2,#4]
;;;395
;;;396 /* Clear HPRE[3:0] bits */
;;;397 tmpreg &= CFGR_HPRE_Reset_Mask;
000004 f02101f0 BIC r1,r1,#0xf0
;;;398
;;;399 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
;;;400 tmpreg |= RCC_SYSCLK;
000008 4301 ORRS r1,r1,r0
;;;401
;;;402 /* Store the new value */
;;;403 RCC->CFGR = tmpreg;
00000a 6051 STR r1,[r2,#4]
;;;404 }
00000c 4770 BX lr
;;;405
ENDP
00000e 0000 DCW 0x0000
|L17.16|
DCD 0x40021000
AREA ||i.RCC_HSEConfig||, CODE, READONLY, ALIGN=2
RCC_HSEConfig PROC
;;;159 *******************************************************************************/
;;;160 void RCC_HSEConfig(u32 RCC_HSE)
000000 490b LDR r1,|L18.48|
;;;161 {
;;;162 /* Check the parameters */
;;;163 assert_param(IS_RCC_HSE(RCC_HSE));
;;;164
;;;165 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
;;;166 /* Reset HSEON bit */
;;;167 RCC->CR &= CR_HSEON_Reset;
000002 680a LDR r2,[r1,#0]
000004 f4223280 BIC r2,r2,#0x10000
000008 600a STR r2,[r1,#0]
;;;168
;;;169 /* Reset HSEBYP bit */
;;;170 RCC->CR &= CR_HSEBYP_Reset;
00000a 680a LDR r2,[r1,#0]
;;;171
;;;172 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
;;;173 switch(RCC_HSE)
00000c f5b03f80 CMP r0,#0x10000
000010 f4222280 BIC r2,r2,#0x40000 ;170
000014 600a STR r2,[r1,#0] ;170
000016 d007 BEQ |L18.40|
000018 f5b02f80 CMP r0,#0x40000
00001c d103 BNE |L18.38|
;;;174 {
;;;175 case RCC_HSE_ON:
;;;176 /* Set HSEON bit */
;;;177 RCC->CR |= CR_HSEON_Set;
;;;178 break;
;;;179
;;;180 case RCC_HSE_Bypass:
;;;181 /* Set HSEBYP and HSEON bits */
;;;182 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
00001e 6808 LDR r0,[r1,#0]
000020 f44020a0 ORR r0,r0,#0x50000
|L18.36|
000024 6008 STR r0,[r1,#0]
|L18.38|
;;;183 break;
;;;184
;;;185 default:
;;;186 break;
;;;187 }
;;;188 }
000026 4770 BX lr
|L18.40|
000028 6808 LDR r0,[r1,#0] ;177
00002a f4403080 ORR r0,r0,#0x10000 ;177
00002e e7f9 B |L18.36|
;;;189
ENDP
|L18.48|
DCD 0x40021000
AREA ||i.RCC_HSICmd||, CODE, READONLY, ALIGN=2
RCC_HSICmd PROC
;;;260 *******************************************************************************/
;;;261 void RCC_HSICmd(FunctionalState NewState)
000000 4901 LDR r1,|L19.8|
;;;262 {
;;;263 /* Check the parameters */
;;;264 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;265
;;;266 *(vu32 *) CR_HSION_BB = (u32)NewState;
000002 6008 STR r0,[r1,#0]
;;;267 }
000004 4770 BX lr
;;;268
ENDP
000006 0000 DCW 0x0000
|L19.8|
DCD 0x42420000
AREA ||i.RCC_ITConfig||, CODE, READONLY, ALIGN=2
RCC_ITConfig PROC
;;;487 *******************************************************************************/
;;;488 void RCC_ITConfig(u8 RCC_IT, FunctionalState NewState)
000000 4a04 LDR r2,|L20.20|
;;;489 {
;;;490 /* Check the parameters */
;;;491 assert_param(IS_RCC_IT(RCC_IT));
;;;492 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;493
;;;494 if (NewState != DISABLE)
000002 2900 CMP r1,#0
;;;495 {
;;;496 /* Perform Byte access to RCC_CIR[12:8] bits to enable the selected interrupts */
;;;497 *(vu8 *) CIR_BYTE2_ADDRESS |= RCC_IT;
000004 7a51 LDRB r1,[r2,#9]
000006 d001 BEQ |L20.12|
000008 4301 ORRS r1,r1,r0
00000a e000 B |L20.14|
|L20.12|
;;;498 }
;;;499 else
;;;500 {
;;;501 /* Perform Byte access to RCC_CIR[12:8] bits to disable the selected interrupts */
;;;502 *(vu8 *) CIR_BYTE2_ADDRESS &= (u8)~RCC_IT;
00000c 4381 BICS r1,r1,r0
|L20.14|
00000e 7251 STRB r1,[r2,#9] ;497
;;;503 }
;;;504 }
000010 4770 BX lr
;;;505
ENDP
000012 0000 DCW 0x0000
|L20.20|
DCD 0x40021000
AREA ||i.RCC_LSEConfig||, CODE, READONLY, ALIGN=2
RCC_LSEConfig PROC
;;;570 *******************************************************************************/
;;;571 void RCC_LSEConfig(u8 RCC_LSE)
000000 4906 LDR r1,|L21.28|
;;;572 {
;;;573 /* Check the parameters */
;;;574 assert_param(IS_RCC_LSE(RCC_LSE));
;;;575
;;;576 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
;;;577 /* Reset LSEON bit */
;;;578 *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
000002 2200 MOVS r2,#0
000004 700a STRB r2,[r1,#0]
;;;579
;;;580 /* Reset LSEBYP bit */
;;;581 *(vu8 *) BDCR_ADDRESS = RCC_LSE_OFF;
000006 f8012920 STRB r2,[r1],#-0x20
;;;582
;;;583 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
;;;584 switch(RCC_LSE)
00000a 2801 CMP r0,#1
00000c d002 BEQ |L21.20|
00000e 2804 CMP r0,#4
000010 d102 BNE |L21.24|
;;;585 {
;;;586 case RCC_LSE_ON:
;;;587 /* Set LSEON bit */
;;;588 *(vu8 *) BDCR_ADDRESS = RCC_LSE_ON;
;;;589 break;
;;;590
;;;591 case RCC_LSE_Bypass:
;;;592 /* Set LSEBYP and LSEON bits */
;;;593 *(vu8 *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
000012 2005 MOVS r0,#5
|L21.20|
000014 f8810020 STRB r0,[r1,#0x20]
|L21.24|
;;;594 break;
;;;595
;;;596 default:
;;;597 break;
;;;598 }
;;;599 }
000018 4770 BX lr
;;;600
ENDP
00001a 0000 DCW 0x0000
|L21.28|
DCD 0x40021020
AREA ||i.RCC_LSICmd||, CODE, READONLY, ALIGN=2
RCC_LSICmd PROC
;;;609 *******************************************************************************/
;;;610 void RCC_LSICmd(FunctionalState NewState)
000000 4901 LDR r1,|L22.8|
;;;611 {
;;;612 /* Check the parameters */
;;;613 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;614
;;;615 *(vu32 *) CSR_LSION_BB = (u32)NewState;
000002 6008 STR r0,[r1,#0]
;;;616 }
000004 4770 BX lr
;;;617
ENDP
000006 0000 DCW 0x0000
|L22.8|
DCD 0x42420480
AREA ||i.RCC_MCOConfig||, CODE, READONLY, ALIGN=2
RCC_MCOConfig PROC
;;;959 *******************************************************************************/
;;;960 void RCC_MCOConfig(u8 RCC_MCO)
000000 4901 LDR r1,|L23.8|
;;;961 {
;;;962 /* Check the parameters */
;;;963 assert_param(IS_RCC_MCO(RCC_MCO));
;;;964
;;;965 /* Perform Byte access to MCO[2:0] bits to select the MCO source */
;;;966 *(vu8 *) CFGR_BYTE4_ADDRESS = RCC_MCO;
000002 71c8 STRB r0,[r1,#7]
;;;967 }
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