📄 stm32f10x_rcc.txt
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;;;1101 *(vu8 *) CIR_BYTE3_ADDRESS = RCC_IT;
000002 7288 STRB r0,[r1,#0xa]
;;;1102 }
000004 4770 BX lr
;;;1103
ENDP
000006 0000 DCW 0x0000
|L10.8|
DCD 0x40021000
AREA ||i.RCC_ClockSecuritySystemCmd||, CODE, READONLY, ALIGN=2
RCC_ClockSecuritySystemCmd PROC
;;;938 *******************************************************************************/
;;;939 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
000000 4901 LDR r1,|L11.8|
;;;940 {
;;;941 /* Check the parameters */
;;;942 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;943
;;;944 *(vu32 *) CR_CSSON_BB = (u32)NewState;
000002 64c8 STR r0,[r1,#0x4c]
;;;945 }
000004 4770 BX lr
;;;946
ENDP
000006 0000 DCW 0x0000
|L11.8|
DCD 0x42420000
AREA ||i.RCC_DeInit||, CODE, READONLY, ALIGN=2
RCC_DeInit PROC
;;;124 *******************************************************************************/
;;;125 void RCC_DeInit(void)
000000 480b LDR r0,|L12.48|
;;;126 {
;;;127 /* Set HSION bit */
;;;128 RCC->CR |= (u32)0x00000001;
000002 6801 LDR r1,[r0,#0]
000004 f0410101 ORR r1,r1,#1
000008 6001 STR r1,[r0,#0]
;;;129
;;;130 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits */
;;;131 RCC->CFGR &= (u32)0xF8FF0000;
00000a 6841 LDR r1,[r0,#4]
00000c 4a09 LDR r2,|L12.52|
00000e 4011 ANDS r1,r1,r2
000010 6041 STR r1,[r0,#4]
;;;132
;;;133 /* Reset HSEON, CSSON and PLLON bits */
;;;134 RCC->CR &= (u32)0xFEF6FFFF;
000012 6801 LDR r1,[r0,#0]
000014 4a08 LDR r2,|L12.56|
000016 4011 ANDS r1,r1,r2
000018 6001 STR r1,[r0,#0]
;;;135
;;;136 /* Reset HSEBYP bit */
;;;137 RCC->CR &= (u32)0xFFFBFFFF;
00001a 6801 LDR r1,[r0,#0]
00001c f4212180 BIC r1,r1,#0x40000
000020 6001 STR r1,[r0,#0]
;;;138
;;;139 /* Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits */
;;;140 RCC->CFGR &= (u32)0xFF80FFFF;
000022 6842 LDR r2,[r0,#4]
;;;141
;;;142 /* Disable all interrupts */
;;;143 RCC->CIR = 0x00000000;
000024 2100 MOVS r1,#0
000026 f42202fe BIC r2,r2,#0x7f0000 ;140
00002a 6042 STR r2,[r0,#4] ;140
00002c 6081 STR r1,[r0,#8]
;;;144 }
00002e 4770 BX lr
;;;145
ENDP
|L12.48|
DCD 0x40021000
|L12.52|
DCD 0xf8ff0000
|L12.56|
DCD 0xfef6ffff
AREA ||i.RCC_GetClocksFreq||, CODE, READONLY, ALIGN=2
RCC_GetClocksFreq PROC
;;;666 *******************************************************************************/
;;;667 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
000000 b510 PUSH {r4,lr}
;;;668 {
;;;669 u32 tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
;;;670
;;;671 /* Get SYSCLK source -------------------------------------------------------*/
;;;672 tmp = RCC->CFGR & CFGR_SWS_Mask;
000002 4a20 LDR r2,|L13.132|
000004 6851 LDR r1,[r2,#4]
;;;673
;;;674 switch (tmp)
;;;675 {
;;;676 case 0x00: /* HSI used as system clock */
;;;677 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
000006 4b20 LDR r3,|L13.136|
000008 f011010c ANDS r1,r1,#0xc ;672
00000c d003 BEQ |L13.22|
00000e 2904 CMP r1,#4 ;674
000010 d001 BEQ |L13.22|
000012 2908 CMP r1,#8 ;674
000014 d001 BEQ |L13.26|
|L13.22|
;;;678 break;
000016 6003 STR r3,[r0,#0]
000018 e011 B |L13.62|
|L13.26|
;;;679
;;;680 case 0x04: /* HSE used as system clock */
;;;681 RCC_Clocks->SYSCLK_Frequency = HSE_Value;
;;;682 break;
;;;683
;;;684 case 0x08: /* PLL used as system clock */
;;;685 /* Get PLL clock source and multiplication factor ----------------------*/
;;;686 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
00001a 6851 LDR r1,[r2,#4]
;;;687 pllmull = ( pllmull >> 18) + 2;
00001c 2302 MOVS r3,#2
00001e f4011170 AND r1,r1,#0x3c0000 ;686
000022 eb034191 ADD r1,r3,r1,LSR #18
;;;688
;;;689 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
000026 6853 LDR r3,[r2,#4]
000028 f4133f80 TST r3,#0x10000
;;;690
;;;691 if (pllsource == 0x00)
00002c d002 BEQ |L13.52|
;;;692 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
;;;693 RCC_Clocks->SYSCLK_Frequency = (HSI_Value >> 1) * pllmull;
;;;694 }
;;;695 else
;;;696 {/* HSE selected as PLL clock entry */
;;;697
;;;698 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (u32)RESET)
00002e 6853 LDR r3,[r2,#4]
000030 039b LSLS r3,r3,#14
000032 d501 BPL |L13.56|
|L13.52|
000034 4b15 LDR r3,|L13.140|
000036 e000 B |L13.58|
|L13.56|
;;;699 {/* HSE oscillator clock divided by 2 */
;;;700
;;;701 RCC_Clocks->SYSCLK_Frequency = (HSE_Value >> 1) * pllmull;
;;;702 }
;;;703 else
;;;704 {
;;;705 RCC_Clocks->SYSCLK_Frequency = HSE_Value * pllmull;
000038 4b13 LDR r3,|L13.136|
|L13.58|
00003a 4359 MULS r1,r3,r1 ;701
00003c 6001 STR r1,[r0,#0] ;701
|L13.62|
;;;706 }
;;;707 }
;;;708 break;
;;;709
;;;710 default:
;;;711 RCC_Clocks->SYSCLK_Frequency = HSI_Value;
;;;712 break;
;;;713 }
;;;714
;;;715 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
;;;716 /* Get HCLK prescaler */
;;;717 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
00003e 6851 LDR r1,[r2,#4]
;;;718 tmp = tmp >> 4;
;;;719 presc = APBAHBPrescTable[tmp];
000040 4b13 LDR r3,|L13.144|
000042 f00101f0 AND r1,r1,#0xf0 ;717
000046 0909 LSRS r1,r1,#4 ;718
000048 5c5c LDRB r4,[r3,r1]
;;;720
;;;721 /* HCLK clock frequency */
;;;722 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
00004a 6801 LDR r1,[r0,#0]
00004c 40e1 LSRS r1,r1,r4
;;;723
;;;724 /* Get PCLK1 prescaler */
;;;725 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
00004e 6041 STR r1,[r0,#4]
000050 6854 LDR r4,[r2,#4]
000052 f40464e0 AND r4,r4,#0x700
;;;726 tmp = tmp >> 8;
000056 0a24 LSRS r4,r4,#8
;;;727 presc = APBAHBPrescTable[tmp];
000058 5d1c LDRB r4,[r3,r4]
;;;728
;;;729 /* PCLK1 clock frequency */
;;;730 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
00005a fa21f404 LSR r4,r1,r4
;;;731
;;;732 /* Get PCLK2 prescaler */
;;;733 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
00005e 6084 STR r4,[r0,#8]
000060 6854 LDR r4,[r2,#4]
000062 f4045460 AND r4,r4,#0x3800
;;;734 tmp = tmp >> 11;
000066 0ae4 LSRS r4,r4,#11
;;;735 presc = APBAHBPrescTable[tmp];
000068 5d1b LDRB r3,[r3,r4]
;;;736
;;;737 /* PCLK2 clock frequency */
;;;738 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
00006a 40d9 LSRS r1,r1,r3
;;;739
;;;740 /* Get ADCCLK prescaler */
;;;741 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
00006c 60c1 STR r1,[r0,#0xc]
00006e 6852 LDR r2,[r2,#4]
;;;742 tmp = tmp >> 14;
;;;743 presc = ADCPrescTable[tmp];
000070 4b07 LDR r3,|L13.144|
000072 f4024240 AND r2,r2,#0xc000 ;741
000076 0b92 LSRS r2,r2,#14 ;742
000078 1f1b SUBS r3,r3,#4
00007a 5c9a LDRB r2,[r3,r2]
;;;744
;;;745 /* ADCCLK clock frequency */
;;;746 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
00007c fbb1f1f2 UDIV r1,r1,r2
;;;747 }
000080 6101 STR r1,[r0,#0x10]
000082 bd10 POP {r4,pc}
;;;748
ENDP
|L13.132|
DCD 0x40021000
|L13.136|
DCD 0x007a1200
|L13.140|
DCD 0x003d0900
|L13.144|
DCD ||.constdata||+0x4
AREA ||i.RCC_GetFlagStatus||, CODE, READONLY, ALIGN=2
RCC_GetFlagStatus PROC
;;;987 *******************************************************************************/
;;;988 FlagStatus RCC_GetFlagStatus(u8 RCC_FLAG)
000000 4603 MOV r3,r0
;;;989 {
;;;990 u32 tmp = 0;
;;;991 u32 statusreg = 0;
;;;992 FlagStatus bitstatus = RESET;
000002 2000 MOVS r0,#0
;;;993
;;;994 /* Check the parameters */
;;;995 assert_param(IS_RCC_FLAG(RCC_FLAG));
;;;996
;;;997 /* Get the RCC register index */
;;;998 tmp = RCC_FLAG >> 5;
000004 0959 LSRS r1,r3,#5
;;;999
;;;1000 if (tmp == 1) /* The flag to check is in CR register */
;;;1001 {
;;;1002 statusreg = RCC->CR;
000006 4a09 LDR r2,|L14.44|
000008 2901 CMP r1,#1 ;1000
00000a d101 BNE |L14.16|
00000c 6811 LDR r1,[r2,#0]
00000e e004 B |L14.26|
|L14.16|
;;;1003 }
;;;1004 else if (tmp == 2) /* The flag to check is in BDCR register */
000010 2902 CMP r1,#2
000012 d101 BNE |L14.24|
;;;1005 {
;;;1006 statusreg = RCC->BDCR;
000014 6a11 LDR r1,[r2,#0x20]
000016 e000 B |L14.26|
|L14.24|
;;;1007 }
;;;1008 else /* The flag to check is in CSR register */
;;;1009 {
;;;1010 statusreg = RCC->CSR;
000018 6a51 LDR r1,[r2,#0x24]
|L14.26|
;;;1011 }
;;;1012
;;;1013 /* Get the flag position */
;;;1014 tmp = RCC_FLAG & FLAG_Mask;
00001a f003021f AND r2,r3,#0x1f
;;;1015
;;;1016 if ((statusreg & ((u32)1 << tmp)) != (u32)RESET)
00001e 2301 MOVS r3,#1
000020 4093 LSLS r3,r3,r2
000022 420b TST r3,r1
000024 d000 BEQ |L14.40|
;;;1017 {
;;;1018 bitstatus = SET;
000026 2001 MOVS r0,#1
|L14.40|
;;;1019 }
;;;1020 else
;;;1021 {
;;;1022 bitstatus = RESET;
;;;1023 }
;;;1024
;;;1025 /* Return the flag status */
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