📄 stm32f10x_nvic.txt
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ENDP
AREA ||i.NVIC_SCBDeInit||, CODE, READONLY, ALIGN=2
NVIC_SCBDeInit PROC
;;;58 *******************************************************************************/
;;;59 void NVIC_SCBDeInit(void)
000000 4a0e LDR r2,|L21.60|
;;;60 {
;;;61 u32 index = 0x00;
;;;62
;;;63 SCB->ICSR = 0x0A000000;
000002 f04f6120 MOV r1,#0xa000000
000006 2000 MOVS r0,#0 ;61
000008 6011 STR r1,[r2,#0]
;;;64 SCB->VTOR = 0x00000000;
00000a 4601 MOV r1,r0
00000c 6050 STR r0,[r2,#4]
;;;65 SCB->AIRCR = AIRCR_VECTKEY_MASK;
00000e 4b0c LDR r3,|L21.64|
000010 6093 STR r3,[r2,#8]
;;;66 SCB->SCR = 0x00000000;
000012 60d0 STR r0,[r2,#0xc]
;;;67 SCB->CCR = 0x00000000;
000014 6110 STR r0,[r2,#0x10]
000016 f6a25204 SUB r2,r2,#0xd04
;;;68 for(index = 0; index < 0x03; index++)
;;;69 {
;;;70 SCB->SHPR[index] = 0;
00001a bf00 NOP
|L21.28|
00001c eb020380 ADD r3,r2,r0,LSL #2
000020 f8c31d18 STR r1,[r3,#0xd18]
000024 1c40 ADDS r0,r0,#1 ;68
000026 2803 CMP r0,#3 ;68
000028 d3f8 BCC |L21.28|
00002a f6025224 ADD r2,r2,#0xd24 ;68
;;;71 }
;;;72 SCB->SHCSR = 0x00000000;
00002e 6011 STR r1,[r2,#0]
;;;73 SCB->CFSR = 0xFFFFFFFF;
000030 f04f30ff MOV r0,#0xffffffff
000034 6050 STR r0,[r2,#4]
;;;74 SCB->HFSR = 0xFFFFFFFF;
000036 6090 STR r0,[r2,#8]
;;;75 SCB->DFSR = 0xFFFFFFFF;
000038 60d0 STR r0,[r2,#0xc]
;;;76 }
00003a 4770 BX lr
;;;77
ENDP
|L21.60|
DCD 0xe000ed04
|L21.64|
DCD 0x05fa0000
AREA ||i.NVIC_SETFAULTMASK||, CODE, READONLY, ALIGN=1
NVIC_SETFAULTMASK PROC
;;;207 *******************************************************************************/
;;;208 void NVIC_SETFAULTMASK(void)
000000 f7ffbffe B.W __SETFAULTMASK
;;;209 {
;;;210 __SETFAULTMASK();
;;;211 }
;;;212
ENDP
AREA ||i.NVIC_SETPRIMASK||, CODE, READONLY, ALIGN=1
NVIC_SETPRIMASK PROC
;;;183 *******************************************************************************/
;;;184 void NVIC_SETPRIMASK(void)
000000 f7ffbffe B.W __SETPRIMASK
;;;185 {
;;;186 __SETPRIMASK();
;;;187 }
;;;188
ENDP
AREA ||i.NVIC_SetIRQChannelPendingBit||, CODE, READONLY, ALIGN=2
NVIC_SetIRQChannelPendingBit PROC
;;;301 *******************************************************************************/
;;;302 void NVIC_SetIRQChannelPendingBit(u8 NVIC_IRQChannel)
000000 4901 LDR r1,|L24.8|
;;;303 {
;;;304 /* Check the parameters */
;;;305 assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
;;;306
;;;307 *(vu32*) 0xE000EF00 = (u32)NVIC_IRQChannel;
000002 6008 STR r0,[r1,#0]
;;;308 }
000004 4770 BX lr
;;;309
ENDP
000006 0000 DCW 0x0000
|L24.8|
DCD 0xe000ef00
AREA ||i.NVIC_SetSystemHandlerPendingBit||, CODE, READONLY, ALIGN=2
NVIC_SetSystemHandlerPendingBit PROC
;;;589 *******************************************************************************/
;;;590 void NVIC_SetSystemHandlerPendingBit(u32 SystemHandler)
000000 4904 LDR r1,|L25.20|
;;;591 {
;;;592 u32 tmp = 0x00;
;;;593
;;;594 /* Check the parameters */
;;;595 assert_param(IS_SET_PENDING_SYSTEM_HANDLER(SystemHandler));
;;;596
;;;597 /* Get the System Handler pending bit position */
;;;598 tmp = SystemHandler & (u32)0x1F;
000002 f000001f AND r0,r0,#0x1f
;;;599 /* Set the corresponding System Handler pending bit */
;;;600 SCB->ICSR |= ((u32)0x01 << tmp);
000006 680b LDR r3,[r1,#0]
000008 2201 MOVS r2,#1
00000a 4082 LSLS r2,r2,r0
00000c 4313 ORRS r3,r3,r2
00000e 600b STR r3,[r1,#0]
;;;601 }
000010 4770 BX lr
;;;602
ENDP
000012 0000 DCW 0x0000
|L25.20|
DCD 0xe000ed04
AREA ||i.NVIC_SetVectorTable||, CODE, READONLY, ALIGN=2
NVIC_SetVectorTable PROC
;;;392 *******************************************************************************/
;;;393 void NVIC_SetVectorTable(u32 NVIC_VectTab, u32 Offset)
000000 4a02 LDR r2,|L26.12|
;;;394 {
;;;395 /* Check the parameters */
;;;396 assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
;;;397 assert_param(IS_NVIC_OFFSET(Offset));
;;;398
;;;399 SCB->VTOR = NVIC_VectTab | (Offset & (u32)0x1FFFFF80);
000002 4011 ANDS r1,r1,r2
000004 4301 ORRS r1,r1,r0
000006 4802 LDR r0,|L26.16|
000008 6001 STR r1,[r0,#0]
;;;400 }
00000a 4770 BX lr
;;;401
ENDP
|L26.12|
DCD 0x1fffff80
|L26.16|
DCD 0xe000ed08
AREA ||i.NVIC_StructInit||, CODE, READONLY, ALIGN=1
NVIC_StructInit PROC
;;;167 *******************************************************************************/
;;;168 void NVIC_StructInit(NVIC_InitTypeDef* NVIC_InitStruct)
000000 2100 MOVS r1,#0
;;;169 {
;;;170 /* NVIC_InitStruct members default value */
;;;171 NVIC_InitStruct->NVIC_IRQChannel = 0x00;
000002 7001 STRB r1,[r0,#0]
;;;172 NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority = 0x00;
000004 7041 STRB r1,[r0,#1]
;;;173 NVIC_InitStruct->NVIC_IRQChannelSubPriority = 0x00;
000006 7081 STRB r1,[r0,#2]
;;;174 NVIC_InitStruct->NVIC_IRQChannelCmd = DISABLE;
000008 70c1 STRB r1,[r0,#3]
;;;175 }
00000a 4770 BX lr
;;;176
ENDP
AREA ||i.NVIC_SystemHandlerConfig||, CODE, READONLY, ALIGN=1
NVIC_SystemHandlerConfig PROC
;;;469 *******************************************************************************/
;;;470 void NVIC_SystemHandlerConfig(u32 SystemHandler, FunctionalState NewState)
000000 f000021f AND r2,r0,#0x1f
;;;471 {
;;;472 u32 tmpreg = 0x00;
;;;473
;;;474 /* Check the parameters */
;;;475 assert_param(IS_CONFIG_SYSTEM_HANDLER(SystemHandler));
;;;476 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;477
;;;478 tmpreg = (u32)0x01 << (SystemHandler & (u32)0x1F);
000004 2001 MOVS r0,#1
000006 4090 LSLS r0,r0,r2
;;;479
;;;480 if (NewState != DISABLE)
;;;481 {
;;;482 SCB->SHCSR |= tmpreg;
000008 f04f22e0 MOV r2,#0xe000e000
00000c 2900 CMP r1,#0 ;480
00000e f8d21d24 LDR r1,[r2,#0xd24]
000012 d001 BEQ |L28.24|
000014 4301 ORRS r1,r1,r0
000016 e000 B |L28.26|
|L28.24|
;;;483 }
;;;484 else
;;;485 {
;;;486 SCB->SHCSR &= ~tmpreg;
000018 4381 BICS r1,r1,r0
|L28.26|
00001a f8c21d24 STR r1,[r2,#0xd24] ;482
;;;487 }
;;;488 }
00001e 4770 BX lr
;;;489
ENDP
AREA ||i.NVIC_SystemHandlerPriorityConfig||, CODE, READONLY, ALIGN=1
NVIC_SystemHandlerPriorityConfig PROC
;;;509 *******************************************************************************/
;;;510 void NVIC_SystemHandlerPriorityConfig(u32 SystemHandler, u8 SystemHandlerPreemptionPriority,
000000 b570 PUSH {r4-r6,lr}
;;;511 u8 SystemHandlerSubPriority)
;;;512 {
;;;513 u32 tmp1 = 0x00, tmp2 = 0xFF, handlermask = 0x00;
;;;514 u32 tmppriority = 0x00;
;;;515
;;;516 /* Check the parameters */
;;;517 assert_param(IS_PRIORITY_SYSTEM_HANDLER(SystemHandler));
;;;518 assert_param(IS_NVIC_PREEMPTION_PRIORITY(SystemHandlerPreemptionPriority));
;;;519 assert_param(IS_NVIC_SUB_PRIORITY(SystemHandlerSubPriority));
;;;520
;;;521 tmppriority = (0x700 - (SCB->AIRCR & (u32)0x700))>> 0x08;
000002 f04f25e0 MOV r5,#0xe000e000
000006 f8d53d0c LDR r3,[r5,#0xd0c]
00000a 24ff MOVS r4,#0xff ;513
00000c f40363e0 AND r3,r3,#0x700
000010 f5c363e0 RSB r3,r3,#0x700
000014 0a1b LSRS r3,r3,#8
;;;522 tmp1 = (0x4 - tmppriority);
;;;523 tmp2 = tmp2 >> tmppriority;
000016 40dc LSRS r4,r4,r3
000018 f1c30604 RSB r6,r3,#4 ;522
;;;524
;;;525 tmppriority = (u32)SystemHandlerPreemptionPriority << tmp1;
00001c 40b1 LSLS r1,r1,r6
;;;526 tmppriority |= SystemHandlerSubPriority & tmp2;
00001e 4022 ANDS r2,r2,r4
000020 430a ORRS r2,r2,r1
000022 0111 LSLS r1,r2,#4
;;;527
;;;528 tmppriority = tmppriority << 0x04;
;;;529 tmp1 = SystemHandler & (u32)0xC0;
000024 f00002c0 AND r2,r0,#0xc0
;;;530 tmp1 = tmp1 >> 0x06;
000028 0992 LSRS r2,r2,#6
;;;531 tmp2 = (SystemHandler >> 0x08) & (u32)0x03;
00002a f3c02001 UBFX r0,r0,#8,#2
;;;532 tmppriority = tmppriority << (tmp2 * 0x08);
00002e 00c0 LSLS r0,r0,#3
000030 4081 LSLS r1,r1,r0
;;;533 handlermask = (u32)0xFF << (tmp2 * 0x08);
000032 23ff MOVS r3,#0xff
000034 4083 LSLS r3,r3,r0
;;;534
;;;535 SCB->SHPR[tmp1] &= ~handlermask;
000036 eb050082 ADD r0,r5,r2,LSL #2
00003a f6005018 ADD r0,r0,#0xd18
00003e 6802 LDR r2,[r0,#0]
000040 439a BICS r2,r2,r3
000042 6002 STR r2,[r0,#0]
;;;536 SCB->SHPR[tmp1] |= tmppriority;
000044 6802 LDR r2,[r0,#0]
000046 430a ORRS r2,r2,r1
000048 6002 STR r2,[r0,#0]
;;;537 }
00004a bd70 POP {r4-r6,pc}
;;;538
ENDP
AREA ||i.NVIC_SystemLPConfig||, CODE, READONLY, ALIGN=1
NVIC_SystemLPConfig PROC
;;;439 *******************************************************************************/
;;;440 void NVIC_SystemLPConfig(u8 LowPowerMode, FunctionalState NewState)
000000 f04f22e0 MOV r2,#0xe000e000
;;;441 {
;;;442 /* Check the parameters */
;;;443 assert_param(IS_NVIC_LP(LowPowerMode));
;;;444 assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;445
;;;446 if (NewState != DISABLE)
000004 2900 CMP r1,#0
;;;447 {
;;;448 SCB->SCR |= LowPowerMode;
000006 f8d21d10 LDR r1,[r2,#0xd10]
00000a d001 BEQ |L30.16|
00000c 4301 ORRS r1,r1,r0
00000e e000 B |L30.18|
|L30.16|
;;;449 }
;;;450 else
;;;451 {
;;;452 SCB->SCR &= (u32)(~(u32)LowPowerMode);
000010 4381 BICS r1,r1,r0
|L30.18|
000012 f8c21d10 STR r1,[r2,#0xd10] ;448
;;;453 }
;;;454 }
000016 4770 BX lr
;;;455
ENDP
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