📄 stm32f10x_nvic.txt
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; generated by ARM C/C++ Compiler with , RVCT4.0 [Build 524] for uVision
; commandline ArmCC [--split_sections --debug -c --asm --interleave -o.\Obj\stm32f10x_nvic.o --depend=.\Obj\stm32f10x_nvic.d --device=DARMSTM --apcs=interwork -O3 -I..\..\include -I..\..\..\FWLib\library\inc -I..\..\..\USBLib\library\inc -I..\..\Config -I..\..\GUI\Core -I..\..\GUI\Font -I..\..\GUI\ConvertColor -I..\..\GUI\AntiAlias -I..\..\GUI\ConvertMono -I..\..\GUI\JPEG -I..\..\GUI\MemDev -I..\..\GUI\MultiLayer -I..\..\GUI\Widget -I..\..\GUI\WM -IC:\Keil\ARM\INC\ST\STM32F10x ..\..\..\FWLib\library\src\stm32f10x_nvic.c]
THUMB
AREA ||i.NVIC_BASEPRICONFIG||, CODE, READONLY, ALIGN=1
NVIC_BASEPRICONFIG PROC
;;;233 *******************************************************************************/
;;;234 void NVIC_BASEPRICONFIG(u32 NewPriority)
000000 0100 LSLS r0,r0,#4
;;;235 {
;;;236 /* Check the parameters */
;;;237 assert_param(IS_NVIC_BASE_PRI(NewPriority));
;;;238
;;;239 __BASEPRICONFIG(NewPriority << 0x04);
000002 f7ffbffe B.W __BASEPRICONFIG
;;;240 }
;;;241
ENDP
AREA ||i.NVIC_ClearIRQChannelPendingBit||, CODE, READONLY, ALIGN=1
NVIC_ClearIRQChannelPendingBit PROC
;;;316 *******************************************************************************/
;;;317 void NVIC_ClearIRQChannelPendingBit(u8 NVIC_IRQChannel)
000000 f000021f AND r2,r0,#0x1f
;;;318 {
;;;319 /* Check the parameters */
;;;320 assert_param(IS_NVIC_IRQ_CHANNEL(NVIC_IRQChannel));
;;;321
;;;322 NVIC->ICPR[(NVIC_IRQChannel >> 0x05)] = (u32)0x01 << (NVIC_IRQChannel & (u32)0x1F);
000004 2101 MOVS r1,#1
000006 4091 LSLS r1,r1,r2
000008 0940 LSRS r0,r0,#5
00000a f04f22e0 MOV r2,#0xe000e000
00000e eb020080 ADD r0,r2,r0,LSL #2
000012 f8c01280 STR r1,[r0,#0x280]
;;;323 }
000016 4770 BX lr
;;;324
ENDP
AREA ||i.NVIC_ClearSystemHandlerPendingBit||, CODE, READONLY, ALIGN=2
NVIC_ClearSystemHandlerPendingBit PROC
;;;613 *******************************************************************************/
;;;614 void NVIC_ClearSystemHandlerPendingBit(u32 SystemHandler)
000000 4b04 LDR r3,|L3.20|
;;;615 {
;;;616 u32 tmp = 0x00;
;;;617
;;;618 /* Check the parameters */
;;;619 assert_param(IS_CLEAR_SYSTEM_HANDLER(SystemHandler));
;;;620
;;;621 /* Get the System Handler pending bit position */
;;;622 tmp = SystemHandler & (u32)0x1F;
000002 f000001f AND r0,r0,#0x1f
;;;623 /* Clear the corresponding System Handler pending bit */
;;;624 SCB->ICSR |= ((u32)0x01 << (tmp - 0x01));
000006 6819 LDR r1,[r3,#0]
000008 1e40 SUBS r0,r0,#1
00000a 2201 MOVS r2,#1
00000c 4082 LSLS r2,r2,r0
00000e 4311 ORRS r1,r1,r2
000010 6019 STR r1,[r3,#0]
;;;625 }
000012 4770 BX lr
;;;626
ENDP
|L3.20|
DCD 0xe000ed04
AREA ||i.NVIC_DeInit||, CODE, READONLY, ALIGN=1
NVIC_DeInit PROC
;;;35 *******************************************************************************/
;;;36 void NVIC_DeInit(void)
000000 2000 MOVS r0,#0
;;;37 {
;;;38 u32 index = 0;
;;;39
;;;40 NVIC->ICER[0] = 0xFFFFFFFF;
000002 1e41 SUBS r1,r0,#1
000004 f04f22e0 MOV r2,#0xe000e000
000008 f8c21180 STR r1,[r2,#0x180]
;;;41 NVIC->ICER[1] = 0x0FFFFFFF;
00000c 090b LSRS r3,r1,#4
00000e f8c23184 STR r3,[r2,#0x184]
;;;42 NVIC->ICPR[0] = 0xFFFFFFFF;
000012 f8c21280 STR r1,[r2,#0x280]
;;;43 NVIC->ICPR[1] = 0x0FFFFFFF;
000016 f8c23284 STR r3,[r2,#0x284]
00001a 4601 MOV r1,r0 ;38
|L4.28|
;;;44
;;;45 for(index = 0; index < 0x0F; index++)
;;;46 {
;;;47 NVIC->IPR[index] = 0x00000000;
00001c eb020380 ADD r3,r2,r0,LSL #2
000020 f8c31400 STR r1,[r3,#0x400]
000024 1c40 ADDS r0,r0,#1 ;45
000026 280f CMP r0,#0xf ;45
000028 d3f8 BCC |L4.28|
;;;48 }
;;;49 }
00002a 4770 BX lr
;;;50
ENDP
AREA ||i.NVIC_GenerateCoreReset||, CODE, READONLY, ALIGN=2
NVIC_GenerateCoreReset PROC
;;;420 *******************************************************************************/
;;;421 void NVIC_GenerateCoreReset(void)
000000 4902 LDR r1,|L5.12|
;;;422 {
;;;423 SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x01;
000002 4801 LDR r0,|L5.8|
000004 6008 STR r0,[r1,#0]
;;;424 }
000006 4770 BX lr
;;;425
ENDP
|L5.8|
DCD 0x05fa0001
|L5.12|
DCD 0xe000ed0c
AREA ||i.NVIC_GenerateSystemReset||, CODE, READONLY, ALIGN=2
NVIC_GenerateSystemReset PROC
;;;408 *******************************************************************************/
;;;409 void NVIC_GenerateSystemReset(void)
000000 4902 LDR r1,|L6.12|
;;;410 {
;;;411 SCB->AIRCR = AIRCR_VECTKEY_MASK | (u32)0x04;
000002 4801 LDR r0,|L6.8|
000004 6008 STR r0,[r1,#0]
;;;412 }
000006 4770 BX lr
;;;413
ENDP
|L6.8|
DCD 0x05fa0004
|L6.12|
DCD 0xe000ed0c
AREA ||i.NVIC_GetBASEPRI||, CODE, READONLY, ALIGN=1
NVIC_GetBASEPRI PROC
;;;248 *******************************************************************************/
;;;249 u32 NVIC_GetBASEPRI(void)
000000 f7ffbffe B.W __GetBASEPRI
;;;250 {
;;;251 return (__GetBASEPRI());
;;;252 }
;;;253
ENDP
AREA ||i.NVIC_GetCPUID||, CODE, READONLY, ALIGN=2
NVIC_GetCPUID PROC
;;;374 *******************************************************************************/
;;;375 u32 NVIC_GetCPUID(void)
000000 4801 LDR r0,|L8.8|
;;;376 {
;;;377 return (SCB->CPUID);
000002 6800 LDR r0,[r0,#0]
;;;378 }
000004 4770 BX lr
;;;379
ENDP
000006 0000 DCW 0x0000
|L8.8|
DCD 0xe000ed00
AREA ||i.NVIC_GetCurrentActiveHandler||, CODE, READONLY, ALIGN=2
NVIC_GetCurrentActiveHandler PROC
;;;332 *******************************************************************************/
;;;333 u16 NVIC_GetCurrentActiveHandler(void)
000000 4802 LDR r0,|L9.12|
;;;334 {
;;;335 return ((u16)(SCB->ICSR & (u32)0x3FF));
000002 6800 LDR r0,[r0,#0]
000004 f3c00009 UBFX r0,r0,#0,#10
;;;336 }
000008 4770 BX lr
;;;337
ENDP
00000a 0000 DCW 0x0000
|L9.12|
DCD 0xe000ed04
AREA ||i.NVIC_GetCurrentPendingIRQChannel||, CODE, READONLY, ALIGN=2
NVIC_GetCurrentPendingIRQChannel PROC
;;;260 *******************************************************************************/
;;;261 u16 NVIC_GetCurrentPendingIRQChannel(void)
000000 4802 LDR r0,|L10.12|
;;;262 {
;;;263 return ((u16)((SCB->ICSR & (u32)0x003FF000) >> 0x0C));
000002 6800 LDR r0,[r0,#0]
000004 f3c03009 UBFX r0,r0,#12,#10
;;;264 }
000008 4770 BX lr
;;;265
ENDP
00000a 0000 DCW 0x0000
|L10.12|
DCD 0xe000ed04
AREA ||i.NVIC_GetFaultAddress||, CODE, READONLY, ALIGN=1
NVIC_GetFaultAddress PROC
;;;729 *******************************************************************************/
;;;730 u32 NVIC_GetFaultAddress(u32 SystemHandler)
000000 f3c05080 UBFX r0,r0,#22,#1
;;;731 {
;;;732 u32 faultaddress = 0x00;
;;;733 u32 tmp = 0x00;
;;;734
;;;735 /* Check the parameters */
;;;736 assert_param(IS_FAULT_ADDRESS_SYSTEM_HANDLER(SystemHandler));
;;;737
;;;738 tmp = (SystemHandler >> 0x16) & (u32)0x01;
;;;739
;;;740 if (tmp == 0x00)
;;;741 {
;;;742 faultaddress = SCB->MMFAR;
000004 f04f21e0 MOV r1,#0xe000e000
000008 b910 CBNZ r0,|L11.16|
00000a f8d10d34 LDR r0,[r1,#0xd34]
;;;743 }
;;;744 else
;;;745 {
;;;746 faultaddress = SCB->BFAR;
;;;747 }
;;;748 return faultaddress;
;;;749 }
00000e 4770 BX lr
|L11.16|
000010 f8d10d38 LDR r0,[r1,#0xd38] ;746
000014 4770 BX lr
;;;750
ENDP
AREA ||i.NVIC_GetFaultHandlerSources||, CODE, READONLY, ALIGN=1
NVIC_GetFaultHandlerSources PROC
;;;683 *******************************************************************************/
;;;684 u32 NVIC_GetFaultHandlerSources(u32 SystemHandler)
000000 f3c04181 UBFX r1,r0,#18,#2
;;;685 {
;;;686 u32 faultsources = 0x00;
;;;687 u32 tmpreg = 0x00, tmppos = 0x00;
;;;688
;;;689 /* Check the parameters */
;;;690 assert_param(IS_FAULT_SOURCE_SYSTEM_HANDLER(SystemHandler));
;;;691
;;;692 tmpreg = (SystemHandler >> 0x12) & (u32)0x03;
;;;693 tmppos = (SystemHandler >> 0x14) & (u32)0x03;
000004 f3c05001 UBFX r0,r0,#20,#2
;;;694
;;;695 if (tmpreg == 0x00)
;;;696 {
;;;697 faultsources = SCB->HFSR;
000008 f04f22e0 MOV r2,#0xe000e000
00000c b911 CBNZ r1,|L12.20|
00000e f8d20d2c LDR r0,[r2,#0xd2c]
;;;698 }
;;;699 else if (tmpreg == 0x01)
;;;700 {
;;;701 faultsources = SCB->CFSR >> (tmppos * 0x08);
;;;702 if (tmppos != 0x02)
;;;703 {
;;;704 faultsources &= (u32)0x0F;
;;;705 }
;;;706 else
;;;707 {
;;;708 faultsources &= (u32)0xFF;
;;;709 }
;;;710 }
;;;711 else
;;;712 {
;;;713 faultsources = SCB->DFSR;
;;;714 }
;;;715 return faultsources;
;;;716 }
000012 4770 BX lr
|L12.20|
000014 2901 CMP r1,#1 ;699
000016 d10b BNE |L12.48|
000018 f8d21d28 LDR r1,[r2,#0xd28] ;701
00001c 00c2 LSLS r2,r0,#3 ;701
00001e 2802 CMP r0,#2 ;702
000020 fa21f102 LSR r1,r1,r2 ;701
000024 d002 BEQ |L12.44|
000026 f001000f AND r0,r1,#0xf ;704
00002a 4770 BX lr
|L12.44|
00002c b2c8 UXTB r0,r1 ;708
00002e 4770 BX lr
|L12.48|
000030 f8d20d30 LDR r0,[r2,#0xd30] ;713
000034 4770 BX lr
;;;717
ENDP
AREA ||i.NVIC_GetIRQChannelActiveBitStatus||, CODE, READONLY, ALIGN=1
NVIC_GetIRQChannelActiveBitStatus PROC
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