stm32f10x_adc.txt

STM32F103ZET6+UCOSII+UCGUI源码

;;;489        /* SWSTART bit is set */
;;;490        bitstatus = SET;
00000a  2001              MOVS     r0,#1
                  |L22.12|
;;;491      }
;;;492      else
;;;493      {
;;;494        /* SWSTART bit is reset */
;;;495        bitstatus = RESET;
;;;496      }
;;;497    
;;;498      /* Return the SWSTART bit status */
;;;499      return  bitstatus;
;;;500    }
00000c  4770              BX       lr
;;;501    
                          ENDP


                          AREA ||i.ADC_GetSoftwareStartInjectedConvCmdStatus||, CODE, READONLY, ALIGN=1

                  ADC_GetSoftwareStartInjectedConvCmdStatus PROC
;;;929    *******************************************************************************/
;;;930    FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
000000  4601              MOV      r1,r0
;;;931    {
;;;932      FlagStatus bitstatus = RESET;
;;;933    
;;;934      /* Check the parameters */
;;;935      assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;936    
;;;937      /* Check the status of JSWSTART bit */
;;;938      if ((ADCx->CR2 & CR2_JSWSTART_Set) != (u32)RESET)
000002  6889              LDR      r1,[r1,#8]
000004  2000              MOVS     r0,#0                 ;932
000006  0289              LSLS     r1,r1,#10
000008  d500              BPL      |L23.12|
;;;939      {
;;;940        /* JSWSTART bit is set */
;;;941        bitstatus = SET;
00000a  2001              MOVS     r0,#1
                  |L23.12|
;;;942      }
;;;943      else
;;;944      {
;;;945        /* JSWSTART bit is reset */
;;;946        bitstatus = RESET;
;;;947      }
;;;948    
;;;949      /* Return the JSWSTART bit status */
;;;950      return  bitstatus;
;;;951    }
00000c  4770              BX       lr
;;;952    
                          ENDP


                          AREA ||i.ADC_ITConfig||, CODE, READONLY, ALIGN=1

                  ADC_ITConfig PROC
;;;326    *******************************************************************************/
;;;327    void ADC_ITConfig(ADC_TypeDef* ADCx, u16 ADC_IT, FunctionalState NewState)
000000  2a00              CMP      r2,#0
;;;328    {
;;;329      u8 itmask = 0;
;;;330    
;;;331      /* Check the parameters */
;;;332      assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;333      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;334      assert_param(IS_ADC_IT(ADC_IT));
;;;335    
;;;336      /* Get the ADC IT index */
;;;337      itmask = (u8)ADC_IT;
;;;338    
;;;339      if (NewState != DISABLE)
;;;340      {
;;;341        /* Enable the selected ADC interrupts */
;;;342        ADCx->CR1 |= itmask;
000002  6842              LDR      r2,[r0,#4]
000004  b2c9              UXTB     r1,r1                 ;337
000006  d001              BEQ      |L24.12|
000008  430a              ORRS     r2,r2,r1
00000a  e000              B        |L24.14|
                  |L24.12|
;;;343      }
;;;344      else
;;;345      {
;;;346        /* Disable the selected ADC interrupts */
;;;347        ADCx->CR1 &= (~(u32)itmask);
00000c  438a              BICS     r2,r2,r1
                  |L24.14|
00000e  6042              STR      r2,[r0,#4]            ;342
;;;348      }
;;;349    }
000010  4770              BX       lr
;;;350    
                          ENDP


                          AREA ||i.ADC_Init||, CODE, READONLY, ALIGN=2

                  ADC_Init PROC
;;;173    ******************************************************************************/
;;;174    void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
000000  b530              PUSH     {r4,r5,lr}
;;;175    {
;;;176      u32 tmpreg1 = 0;
;;;177      u8 tmpreg2 = 0;
;;;178    
;;;179      /* Check the parameters */
;;;180      assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;181      assert_param(IS_ADC_MODE(ADC_InitStruct->ADC_Mode));
;;;182      assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
;;;183      assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));  		    
;;;184      assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));   
;;;185      assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); 
;;;186      assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfChannel));
;;;187    
;;;188      /*---------------------------- ADCx CR1 Configuration -----------------*/
;;;189      /* Get the ADCx CR1 value */
;;;190      tmpreg1 = ADCx->CR1;
000002  6842              LDR      r2,[r0,#4]
;;;191      /* Clear DUALMOD and SCAN bits */
;;;192      tmpreg1 &= CR1_CLEAR_Mask;
000004  4b0e              LDR      r3,|L25.64|
;;;193      /* Configure ADCx: Dual mode and scan conversion mode */
;;;194      /* Set DUALMOD bits according to ADC_Mode value */
;;;195      /* Set SCAN bit according to ADC_ScanConvMode value */
;;;196      tmpreg1 |= (u32)(ADC_InitStruct->ADC_Mode | ((u32)ADC_InitStruct->ADC_ScanConvMode << 8));
000006  790c              LDRB     r4,[r1,#4]
000008  401a              ANDS     r2,r2,r3              ;192
00000a  680b              LDR      r3,[r1,#0]
00000c  ea422204          ORR      r2,r2,r4,LSL #8
000010  4313              ORRS     r3,r3,r2
;;;197      /* Write to ADCx CR1 */
;;;198      ADCx->CR1 = tmpreg1;
000012  6043              STR      r3,[r0,#4]
;;;199    
;;;200      /*---------------------------- ADCx CR2 Configuration -----------------*/
;;;201      /* Get the ADCx CR2 value */
;;;202      tmpreg1 = ADCx->CR2;
000014  6882              LDR      r2,[r0,#8]
;;;203      /* Clear CONT, ALIGN and EXTSEL bits */
;;;204      tmpreg1 &= CR2_CLEAR_Mask;
000016  4b0b              LDR      r3,|L25.68|
;;;205      /* Configure ADCx: external trigger event and continuous conversion mode */
;;;206      /* Set ALIGN bit according to ADC_DataAlign value */
;;;207      /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
;;;208      /* Set CONT bit according to ADC_ContinuousConvMode value */
;;;209      tmpreg1 |= (u32)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
000018  794d              LDRB     r5,[r1,#5]
00001a  401a              ANDS     r2,r2,r3              ;204
00001c  e9d14302          LDRD     r4,r3,[r1,#8]
000020  ea420245          ORR      r2,r2,r5,LSL #1
000024  4323              ORRS     r3,r3,r4
000026  4313              ORRS     r3,r3,r2
;;;210                ((u32)ADC_InitStruct->ADC_ContinuousConvMode << 1));
;;;211      /* Write to ADCx CR2 */
;;;212      ADCx->CR2 = tmpreg1;
000028  6083              STR      r3,[r0,#8]
;;;213    
;;;214      /*---------------------------- ADCx SQR1 Configuration -----------------*/
;;;215      /* Get the ADCx SQR1 value */
;;;216      tmpreg1 = ADCx->SQR1;
00002a  6ac2              LDR      r2,[r0,#0x2c]
;;;217      /* Clear L bits */
;;;218      tmpreg1 &= SQR1_CLEAR_Mask;
;;;219      /* Configure ADCx: regular channel sequence length */
;;;220      /* Set L bits according to ADC_NbrOfChannel value */
;;;221      tmpreg2 |= (ADC_InitStruct->ADC_NbrOfChannel - 1);
00002c  7c09              LDRB     r1,[r1,#0x10]
00002e  f4220270          BIC      r2,r2,#0xf00000       ;218
000032  1e49              SUBS     r1,r1,#1
000034  b2c9              UXTB     r1,r1
;;;222      tmpreg1 |= ((u32)tmpreg2 << 20);
000036  ea425101          ORR      r1,r2,r1,LSL #20
;;;223      /* Write to ADCx SQR1 */
;;;224      ADCx->SQR1 = tmpreg1;
00003a  62c1              STR      r1,[r0,#0x2c]
;;;225    }
00003c  bd30              POP      {r4,r5,pc}
;;;226    
                          ENDP

00003e  0000              DCW      0x0000
                  |L25.64|
                          DCD      0xfff0feff
                  |L25.68|
                          DCD      0xfff1f7fd

                          AREA ||i.ADC_InjectedChannelConfig||, CODE, READONLY, ALIGN=1

                  ADC_InjectedChannelConfig PROC
;;;993    *******************************************************************************/
;;;994    void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, u8 ADC_Channel, u8 Rank, u8 ADC_SampleTime)
000000  b570              PUSH     {r4-r6,lr}
;;;995    {
;;;996      u32 tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
;;;997    
;;;998      /* Check the parameters */
;;;999      assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;1000     assert_param(IS_ADC_CHANNEL(ADC_Channel));
;;;1001     assert_param(IS_ADC_INJECTED_RANK(Rank));
;;;1002     assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
;;;1003   
;;;1004     /* if ADC_Channel_10 ... ADC_Channel_17 is selected */
;;;1005     if (ADC_Channel > ADC_Channel_9)
;;;1006     {
;;;1007       /* Get the old register value */
;;;1008       tmpreg1 = ADCx->SMPR1;
;;;1009       /* Calculate the mask to clear */
;;;1010       tmpreg2 = SMPR1_SMP_Set << (3*(ADC_Channel - 10));
000002  2607              MOVS     r6,#7
000004  2909              CMP      r1,#9                 ;1005
000006  d90a              BLS      |L26.30|
000008  68c5              LDR      r5,[r0,#0xc]          ;1008
00000a  f1a1040a          SUB      r4,r1,#0xa
00000e  eb040444          ADD      r4,r4,r4,LSL #1
000012  40a6              LSLS     r6,r6,r4
;;;1011       /* Clear the old discontinuous mode channel count */
;;;1012       tmpreg1 &= ~tmpreg2;
000014  43b5              BICS     r5,r5,r6
;;;1013       /* Calculate the mask to set */
;;;1014       tmpreg2 = (u32)ADC_SampleTime << (3*(ADC_Channel - 10));
000016  40a3              LSLS     r3,r3,r4
;;;1015       /* Set the discontinuous mode channel count */
;;;1016       tmpreg1 |= tmpreg2;
000018  431d              ORRS     r5,r5,r3
;;;1017       /* Store the new register value */
;;;1018       ADCx->SMPR1 = tmpreg1;
00001a  60c5              STR      r5,[r0,#0xc]
00001c  e007              B        |L26.46|
                  |L26.30|
;;;1019     }
;;;1020     else /* ADC_Channel include in ADC_Channel_[0..9] */
;;;1021     {
;;;1022       /* Get the old register value */
;;;1023       tmpreg1 = ADCx->SMPR2;
00001e  6905              LDR      r5,[r0,#0x10]
;;;1024       /* Calculate the mask to clear */
;;;1025       tmpreg2 = SMPR2_SMP_Set << (3 * ADC_Channel);
000020  eb010441          ADD      r4,r1,r1,LSL #1
000024  40a6              LSLS     r6,r6,r4
;;;1026       /* Clear the old discontinuous mode channel count */
;;;1027       tmpreg1 &= ~tmpreg2;
000026  43b5              BICS     r5,r5,r6
;;;1028       /* Calculate the mask to set */
;;;1029       tmpreg2 = (u32)ADC_SampleTime << (3 * ADC_Channel);
000028  40a3              LSLS     r3,r3,r4
;;;1030       /* Set the discontinuous mode channel count */
;;;1031       tmpreg1 |= tmpreg2;
00002a  431d              ORRS     r5,r5,r3
;;;1032       /* Store the new register value */
;;;1033       ADCx->SMPR2 = tmpreg1;
00002c  6105              STR      r5,[r0,#0x10]
                  |L26.46|
;;;1034     }
;;;1035   
;;;1036     /* Rank configuration */
;;;1037     /* Get the old register value */
;;;1038     tmpreg1 = ADCx->JSQR;
00002e  6b83              LDR      r3,[r0,#0x38]
;;;1039     /* Get JL value: Number = JL+1 */
;;;1040     tmpreg3 =  (tmpreg1 & JSQR_JL_Set)>> 20;
000030  f3c35401          UBFX     r4,r3,#20,#2
;;;1041     /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
;;;1042     tmpreg2 = JSQR_JSQ_Set << (5 * (u8)((Rank + 3) - (tmpreg3 + 1)));
000034  1b12              SUBS     r2,r2,r4
000036  1c92              ADDS     r2,r2,#2
000038  eb020282          ADD      r2,r2,r2,LSL #2
00003c  241f              MOVS     r4,#0x1f
00003e  4094              LSLS     r4,r4,r2
;;;1043     /* Clear the old JSQx bits for the selected rank */
;;;1044     tmpreg1 &= ~tmpreg2;
000040  43a3              BICS     r3,r3,r4
;;;1045     /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
;;;1046     tmpreg2 = (u32)ADC_Channel << (5 * (u8)((Rank + 3) - (tmpreg3 + 1)));
000042  4091              LSLS     r1,r1,r2
;;;1047     /* Set the JSQx bits for the selected rank */
;;;1048     tmpreg1 |= tmpreg2;
000044  430b              ORRS     r3,r3,r1
;;;1049     /* Store the new register value */
;;;1050     ADCx->JSQR = tmpreg1;
000046  6383              STR      r3,[r0,#0x38]
;;;1051   }
000048  bd70              POP      {r4-r6,pc}
;;;1052   
                          ENDP


                          AREA ||i.ADC_InjectedDiscModeCmd||, CODE, READONLY, ALIGN=1

                  ADC_InjectedDiscModeCmd PROC
;;;788    *******************************************************************************/
;;;789    void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
000000  2900              CMP      r1,#0
;;;790    {
;;;791      /* Check the parameters */
;;;792      assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;793      assert_param(IS_FUNCTIONAL_STATE(NewState));
;;;794    
;;;795      if (NewState != DISABLE)
;;;796      {
;;;797        /* Enable the selected ADC injected discontinuous mode */
;;;798        ADCx->CR1 |= CR1_JDISCEN_Set;
000002  6841              LDR      r1,[r0,#4]
000004  d002              BEQ      |L27.12|
000006  f4415180          ORR      r1,r1,#0x1000
00000a  e001              B        |L27.16|
                  |L27.12|
;;;799      }
;;;800      else
;;;801      {
;;;802        /* Disable the selected ADC injected discontinuous mode */
;;;803        ADCx->CR1 &= CR1_JDISCEN_Reset;
00000c  f4215180          BIC      r1,r1,#0x1000
                  |L27.16|
000010  6041              STR      r1,[r0,#4]            ;798
;;;804      }
;;;805    }
000012  4770              BX       lr
;;;806    
                          ENDP


                          AREA ||i.ADC_InjectedSequencerLengthConfig||, CODE, READONLY, ALIGN=1

                  ADC_InjectedSequencerLengthConfig PROC
;;;1061   *******************************************************************************/
;;;1062   void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, u8 Length)
000000  6b82              LDR      r2,[r0,#0x38]
;;;1063   {
;;;1064     u32 tmpreg1 = 0;
;;;1065     u32 tmpreg2 = 0;
;;;1066   
;;;1067     /* Check the parameters */
;;;1068     assert_param(IS_ADC_ALL_PERIPH(ADCx));
;;;1069     assert_param(IS_ADC_INJECTED_LENGTH(Length));
;;;1070     
;;;1071     /* Get the old register value */
;;;1072     tmpreg1 = ADCx->JSQR;
;;;1073     /* Clear the old injected sequnence lenght JL bits */
;;;1074     tmpreg1 &= JSQR_JL_Reset;
;;;1075     /* Set the injected sequnence lenght JL bits */
;;;1076     tmpreg2 = Length - 1; 
000002  1e49              SUBS     r1,r1,#1
000004  f4221240          BIC      r2,r2,#0x300000       ;1074
;;;1077     tmpreg1 |= tmpreg2 << 20;
000008  ea425101          ORR      r1,r2,r1,LSL #20
;;;1078     /* Store the new register value */
;;;1079     ADCx->JSQR = tmpreg1;
00000c  6381              STR      r1,[r0,#0x38]
;;;1080   }
00000e  4770              BX       lr
;;;1081   
                          ENDP


                          AREA ||i.ADC_RegularChannelConfig||, CODE, READONLY, ALIGN=1

                  ADC_RegularChannelConfig PROC
;;;601    *******************************************************************************/