📄 fsmc_nand.txt
字号:
|L8.18|
;;;443 }
;;;444 else if((data & NAND_READY) == NAND_READY)
;;;445 {
;;;446 status = NAND_READY;
;;;447 }
;;;448 else
;;;449 {
;;;450 status = NAND_BUSY;
;;;451 }
;;;452
;;;453 return (status);
;;;454 }
000012 4770 BX lr
|L8.20|
000014 0649 LSLS r1,r1,#25 ;444
000016 d5fc BPL |L8.18|
000018 2040 MOVS r0,#0x40 ;446
00001a 4770 BX lr
;;;455
ENDP
|L8.28|
DCD 0x70010000
AREA ||i.FSMC_NAND_Reset||, CODE, READONLY, ALIGN=2
FSMC_NAND_Reset PROC
;;;383 *******************************************************************************/
;;;384 u32 FSMC_NAND_Reset(void)
000000 4902 LDR r1,|L9.12|
;;;385 {
;;;386 *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_RESET;
000002 20ff MOVS r0,#0xff
000004 7008 STRB r0,[r1,#0]
;;;387
;;;388 return (NAND_READY);
000006 2040 MOVS r0,#0x40
;;;389 }
000008 4770 BX lr
;;;390
ENDP
00000a 0000 DCW 0x0000
|L9.12|
DCD 0x70010000
AREA ||i.FSMC_NAND_WriteSmallPage||, CODE, READONLY, ALIGN=2
FSMC_NAND_WriteSmallPage PROC
;;;139 *******************************************************************************/
;;;140 u32 FSMC_NAND_WriteSmallPage(u8 *pBuffer, NAND_ADDRESS Address, u32 NumPageToWrite)
000000 e92d4fff PUSH {r0-r11,lr}
;;;141 {
;;;142 u32 index = 0x00, numpagewritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
000004 2400 MOVS r4,#0
000006 f44f7a80 MOV r10,#0x100
00000a 4681 MOV r9,r0 ;141
00000c 461f MOV r7,r3 ;141
00000e 4626 MOV r6,r4
000010 46d0 MOV r8,r10
;;;143 u32 status = NAND_READY, size = 0x00;
000012 2540 MOVS r5,#0x40
;;;144
;;;145 while((NumPageToWrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
;;;146 {
;;;147 /* Page write command and address */
;;;148 *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_A;
000014 f8dfb07c LDR r11,|L10.148|
000018 e031 B |L10.126|
|L10.26|
00001a 2000 MOVS r0,#0
00001c 4659 MOV r1,r11
00001e f88b0000 STRB r0,[r11,#0]
;;;149 *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
000022 2280 MOVS r2,#0x80
000024 f88b2000 STRB r2,[r11,#0]
;;;150
;;;151 *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
000028 4a1b LDR r2,|L10.152|
00002a 7010 STRB r0,[r2,#0]
;;;152 *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
00002c f8bd0006 LDRH r0,[sp,#6]
000030 f8bd3004 LDRH r3,[sp,#4]
000034 eb002083 ADD r0,r0,r3,LSL #10
000038 f8bd3008 LDRH r3,[sp,#8]
00003c eb031040 ADD r0,r3,r0,LSL #5
000040 7010 STRB r0,[r2,#0]
;;;153 *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
000042 0a03 LSRS r3,r0,#8
000044 7013 STRB r3,[r2,#0]
;;;154 *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
000046 0c00 LSRS r0,r0,#16
000048 7010 STRB r0,[r2,#0]
;;;155
;;;156 /* Calculate the size */
;;;157 size = NAND_PAGE_SIZE + (NAND_PAGE_SIZE * numpagewritten);
00004a f44f7000 MOV r0,#0x200
00004e eb002046 ADD r0,r0,r6,LSL #9
;;;158
;;;159 /* Write data */
;;;160 for(; index < size; index++)
;;;161 {
;;;162 *(vu8 *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
000052 f04f42e0 MOV r2,#0x70000000
000056 e003 B |L10.96|
|L10.88|
000058 f8193004 LDRB r3,[r9,r4]
00005c 7013 STRB r3,[r2,#0]
00005e 1c64 ADDS r4,r4,#1 ;160
|L10.96|
000060 4284 CMP r4,r0 ;160
000062 d3f9 BCC |L10.88|
;;;163 }
;;;164
;;;165 *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
000064 2010 MOVS r0,#0x10
000066 7008 STRB r0,[r1,#0]
;;;166
;;;167 /* Check status for successful operation */
;;;168 status = FSMC_NAND_GetStatus();
000068 f7fffffe BL FSMC_NAND_GetStatus
00006c 4605 MOV r5,r0
;;;169
;;;170 if(status == NAND_READY)
00006e 2840 CMP r0,#0x40
000070 d105 BNE |L10.126|
;;;171 {
;;;172 numpagewritten++;
000072 1c76 ADDS r6,r6,#1
;;;173
;;;174 NumPageToWrite--;
000074 1e7f SUBS r7,r7,#1
;;;175
;;;176 /* Calculate Next small page Address */
;;;177 addressstatus = FSMC_NAND_AddressIncrement(&Address);
000076 a801 ADD r0,sp,#4
000078 f7fffffe BL FSMC_NAND_AddressIncrement
00007c 4680 MOV r8,r0
|L10.126|
00007e b11f CBZ r7,|L10.136|
000080 45d0 CMP r8,r10 ;145
000082 d101 BNE |L10.136|
000084 2d40 CMP r5,#0x40 ;145
000086 d0c8 BEQ |L10.26|
|L10.136|
;;;178 }
;;;179 }
;;;180
;;;181 return (status | addressstatus);
000088 ea450008 ORR r0,r5,r8
;;;182 }
00008c b004 ADD sp,sp,#0x10
00008e e8bd8ff0 POP {r4-r11,pc}
;;;183
ENDP
000092 0000 DCW 0x0000
|L10.148|
DCD 0x70010000
|L10.152|
DCD 0x70020000
AREA ||i.FSMC_NAND_WriteSpareArea||, CODE, READONLY, ALIGN=2
FSMC_NAND_WriteSpareArea PROC
;;;254 *******************************************************************************/
;;;255 u32 FSMC_NAND_WriteSpareArea(u8 *pBuffer, NAND_ADDRESS Address, u32 NumSpareAreaTowrite)
000000 e92d4fff PUSH {r0-r11,lr}
;;;256 {
;;;257 u32 index = 0x00, numsparesreawritten = 0x00, addressstatus = NAND_VALID_ADDRESS;
000004 2400 MOVS r4,#0
000006 f44f7a80 MOV r10,#0x100
00000a 4681 MOV r9,r0 ;256
00000c 461f MOV r7,r3 ;256
00000e 4626 MOV r6,r4
000010 46d0 MOV r8,r10
;;;258 u32 status = NAND_READY, size = 0x00;
000012 2540 MOVS r5,#0x40
;;;259
;;;260 while((NumSpareAreaTowrite != 0x00) && (addressstatus == NAND_VALID_ADDRESS) && (status == NAND_READY))
;;;261 {
;;;262 /* Page write Spare area command and address */
;;;263 *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_AREA_C;
000014 f8dfb078 LDR r11,|L11.144|
000018 e030 B |L11.124|
|L11.26|
00001a 2050 MOVS r0,#0x50
00001c 4659 MOV r1,r11
00001e f88b0000 STRB r0,[r11,#0]
;;;264 *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE0;
000022 2080 MOVS r0,#0x80
000024 f88b0000 STRB r0,[r11,#0]
;;;265
;;;266 *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = 0x00;
000028 4a1a LDR r2,|L11.148|
00002a 2000 MOVS r0,#0
00002c 7010 STRB r0,[r2,#0]
;;;267 *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_1st_CYCLE(ROW_ADDRESS);
00002e f8bd0006 LDRH r0,[sp,#6]
000032 f8bd3004 LDRH r3,[sp,#4]
000036 eb002083 ADD r0,r0,r3,LSL #10
00003a f8bd3008 LDRH r3,[sp,#8]
00003e eb031040 ADD r0,r3,r0,LSL #5
000042 7010 STRB r0,[r2,#0]
;;;268 *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_2nd_CYCLE(ROW_ADDRESS);
000044 0a03 LSRS r3,r0,#8
000046 7013 STRB r3,[r2,#0]
;;;269 *(vu8 *)(Bank_NAND_ADDR | ADDR_AREA) = ADDR_3rd_CYCLE(ROW_ADDRESS);
000048 0c00 LSRS r0,r0,#16
00004a 7010 STRB r0,[r2,#0]
;;;270
;;;271 /* Calculate the size */
;;;272 size = NAND_SPARE_AREA_SIZE + (NAND_SPARE_AREA_SIZE * numsparesreawritten);
00004c 2210 MOVS r2,#0x10
00004e eb021006 ADD r0,r2,r6,LSL #4
;;;273
;;;274 /* Write the data */
;;;275 for(; index < size; index++)
;;;276 {
;;;277 *(vu8 *)(Bank_NAND_ADDR | DATA_AREA) = pBuffer[index];
000052 f04f43e0 MOV r3,#0x70000000
000056 e003 B |L11.96|
|L11.88|
000058 f8195004 LDRB r5,[r9,r4]
00005c 701d STRB r5,[r3,#0]
00005e 1c64 ADDS r4,r4,#1 ;275
|L11.96|
000060 4284 CMP r4,r0 ;275
000062 d3f9 BCC |L11.88|
;;;278 }
;;;279
;;;280 *(vu8 *)(Bank_NAND_ADDR | CMD_AREA) = NAND_CMD_WRITE_TRUE1;
000064 700a STRB r2,[r1,#0]
;;;281
;;;282 /* Check status for successful operation */
;;;283 status = FSMC_NAND_GetStatus();
000066 f7fffffe BL FSMC_NAND_GetStatus
00006a 4605 MOV r5,r0
;;;284
;;;285 if(status == NAND_READY)
00006c 2840 CMP r0,#0x40
00006e d105 BNE |L11.124|
;;;286 {
;;;287 numsparesreawritten++;
000070 1c76 ADDS r6,r6,#1
;;;288
;;;289 NumSpareAreaTowrite--;
000072 1e7f SUBS r7,r7,#1
;;;290
;;;291 /* Calculate Next page Address */
;;;292 addressstatus = FSMC_NAND_AddressIncrement(&Address);
000074 a801 ADD r0,sp,#4
000076 f7fffffe BL FSMC_NAND_AddressIncrement
00007a 4680 MOV r8,r0
|L11.124|
00007c b11f CBZ r7,|L11.134|
00007e 45d0 CMP r8,r10 ;260
000080 d101 BNE |L11.134|
000082 2d40 CMP r5,#0x40 ;260
000084 d0c9 BEQ |L11.26|
|L11.134|
;;;293 }
;;;294 }
;;;295
;;;296 return (status | addressstatus);
000086 ea450008 ORR r0,r5,r8
;;;297 }
00008a b004 ADD sp,sp,#0x10
00008c e8bd8ff0 POP {r4-r11,pc}
;;;298
ENDP
|L11.144|
DCD 0x70010000
|L11.148|
DCD 0x70020000
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